> > Since the 4040 is Async, wont this method risk false triggering
> > as the ripple goes through the stages?
>
> No, and if you think about it a bit, you'll see why.
>
> A ripple counter is made of flip-flops that change state on the
high-to-low
> transition of the clock. So, because of causality, a given stage has to go
> low before the stage that it drives can go high. As a result, you can
never
> see a count that is "too high", even as a glitch; you'll only see glitch
> values that are too low. Therefore, this method of creating a programmable
> divider works just fine.
>
> -- Dave Tweed

I've been the victim of a typo in the Motorola CMOS databook. In the
specs for the 4040 @ 5V

Max clock pulse frequency = 3.5MHz
Propagation Delay time    =  (1.7ns/pF)*CL + 315ns   = 400ns
Clock to Q12                      =  (1.7ns/pF)*CL + 2415ns = 2.5ns
(!!!!!!!!)

The data sheet here

http://www.ee.mut.ac.th/datasheet/MC14040.pdf

gives Clock to Q12 as 1625ns, and Clock Frequency has been
reduced to 2.1MHz

The 74HC4040 would be suitable at 12.5MHz (>28MHz @ 5V and
much shorter propagation delays)

http://www.ee.nmt.edu/~rhb/ee231/labs2000/lab02/mc74hc4040.pdf

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