Jinx wrote:
>> This is a clock for a processor implemented in an fpga. The division
>> comes about because there is a uart implemented as well inside the
>> processor to avoid framing errors. So, yes, it is a square wave. -Vic
>
> You could do it with a 4040 and a 4-input AND gate. Take the logic
> outputs for hA3 = %10100011 (a0,a1,a5,a7) and AND them together,
> with the output going to the 4040's reset to clear the 4040 back to
> all zero outputs. A pulse will be produced each time a0&a1&a5&a7
>
> I use this method to do long division in h/w when counting mains
> cycles but you may find that the 4040 @ 5V won't take 12.5MHz.
> The 74HC4040 probably would, and any TTL binary counter will
>


There is a way to produce a pretty square wave even dividing by 163.

Two 74HC4040, 2 x 74HC11 and 1 x 74HC00 (or an Flip-Flop SR).
Each state of flip-flop route input clock to one of the 4040s.

4040 "A" counts up to 81 sets the FF and resets itself. The FF will then
route clock to the 4040 "B" that will count up to 82 and then resets the FF
and itself. The FF will then route clock back to the first 4040 ("A") and
go on.

The FF output will represent this division by 163 with a simmetry of 49.4%.

Perhaps using more digital gates it is possible to do the same with just
one 4040...

/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Wagner Lipnharski - UST Research Inc
Orlando FLorida - USA - www.ustr.net
/_/_/_/ Atmel AVR Consultant /_/_/_/

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