From PICLIST@MITVMA.MIT.EDU Fri Nov 15 05:10:26 2002 Received: from cherry.ease.lsoft.com [209.119.0.109] by dpmail10.doteasy.com with ESMTP (SMTPD32-7.13) id A242199600EC; Fri, 15 Nov 2002 05:10:26 -0800 Received: from PEAR.EASE.LSOFT.COM (209.119.0.19) by cherry.ease.lsoft.com (LSMTP for Digital Unix v1.1b) with SMTP id <3.007DB85B@cherry.ease.lsoft.com>; Fri, 15 Nov 2002 7:56:18 -0500 Received: from MITVMA.MIT.EDU by MITVMA.MIT.EDU (LISTSERV-TCP/IP release 1.8d) with spool id 1866 for PICLIST@MITVMA.MIT.EDU; Fri, 15 Nov 2002 07:56:09 -0500 Received: from MITVMA (NJE origin SMTP@MITVMA) by MITVMA.MIT.EDU (LMail V1.2d/1.8d) with BSMTP id 8497; Fri, 15 Nov 2002 07:55:19 -0500 Received: from *unknown [206.47.199.164] by mitvma.mit.edu (IBM VM SMTP Level 320) via TCP with SMTP ; Fri, 15 Nov 2002 07:55:18 EST X-Warning: mitvma.mit.edu: Host *unknown claimed to be simmts6-srv.bellnexxia.net Received: from a7m7h6 ([156.34.182.176]) by simmts6-srv.bellnexxia.net (InterMail vM.5.01.04.19 201-253-122-122-119-20020516) with SMTP id <20021115125518.MJGE3900.simmts6-srv.bellnexxia.net@a7m7h6> for ; Fri, 15 Nov 2002 07:55:18 -0500 References: <012301c28c8f$f3b25d80$e7bdf682@sstdwkiwi> MIME-Version: 1.0 Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Message-ID: <010001c28ca5$f6ce4180$b64aa40a@a7m7h6> Date: Fri, 15 Nov 2002 08:53:15 -0400 Reply-To: pic microcontroller discussion list Sender: pic microcontroller discussion list From: Ray Gallant Subject: [PIC]: Detecting SRAM and eeprom To: PICLIST@MITVMA.MIT.EDU X-RCPT-TO: Status: R X-UIDL: 277600641 X-Evolution-Source: pop://mailinglist%40farcite.net@mail.farcite.net/ X-Evolution: 00000756-0000 Do I detect a hint on the topic of TTL , pullups and pulldowns as seen in an old post! {slewrate} ----- Original Message ----- From: "Alan B. Pearce" To: Sent: Friday, November 15, 2002 6:15 AM Subject: Re: [PIC]: Detecting SRAM and eeprom > >The problem is in the read after write to the same location. On many cmos > >buses the bus capacitance will store state between the read and write and > >the test will succeed even if there is no part at that address. I did not > >dream this up, it really happens all the time and I do take this into > >account. >------------------------------- > Which is why it is good ractice to have pull up or pull down resistors, and > when doing such tests always write a pattern with both 1's and 0's in it. >--------------------- >--------------- > One free guess why the standard IBM PC POST writes alternating 0xAA & 0x55 > to adjacent locations. It saves the exact capacitive storage problem you > have just described from affecting the read action. -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.