From PICLIST@MITVMA.MIT.EDU Fri Nov 15 02:27:04 2002 Received: from cherry.ease.lsoft.com [209.119.0.109] by dpmail10.doteasy.com with ESMTP (SMTPD32-7.13) id ABF814C50084; Fri, 15 Nov 2002 02:27:04 -0800 Received: from PEAR.EASE.LSOFT.COM (209.119.0.19) by cherry.ease.lsoft.com (LSMTP for Digital Unix v1.1b) with SMTP id <10.007DB4F7@cherry.ease.lsoft.com>; Fri, 15 Nov 2002 5:13:02 -0500 Received: from MITVMA.MIT.EDU by MITVMA.MIT.EDU (LISTSERV-TCP/IP release 1.8d) with spool id 0451 for PICLIST@MITVMA.MIT.EDU; Fri, 15 Nov 2002 05:12:49 -0500 Received: from MITVMA (NJE origin SMTP@MITVMA) by MITVMA.MIT.EDU (LMail V1.2d/1.8d) with BSMTP id 5833; Fri, 15 Nov 2002 05:11:02 -0500 Received: from nameserv.rl.ac.uk [130.246.135.129] by mitvma.mit.edu (IBM VM SMTP Level 320) via TCP with ESMTP ; Fri, 15 Nov 2002 05:11:01 EST X-Comment: mitvma.mit.edu: Mail was sent by nameserv.rl.ac.uk Received: from sstdwkiwi (sstdwkiwi.ag.rl.ac.uk [130.246.189.231]) by nameserv.rl.ac.uk (8.8.8/8.8.8) with SMTP id KAA27153 for ; Fri, 15 Nov 2002 10:11:01 GMT References: <00e001c28bfc$d5792120$0a01a8c0@djm> <000501c28c18$83fc02b0$0300a8c0@main> <000e01c28c37$65405500$0a01a8c0@djm> <000801c28c46$063aa060$6501a8c0@potshe01.pa.comcast.net> X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4807.1700 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Message-ID: <011401c28c8f$4d1c7dc0$e7bdf682@sstdwkiwi> Date: Fri, 15 Nov 2002 10:11:01 -0000 Reply-To: pic microcontroller discussion list Sender: pic microcontroller discussion list From: "Alan B. Pearce" Subject: Re: [PIC]:failed data location? To: PICLIST@MITVMA.MIT.EDU X-RCPT-TO: Status: R X-UIDL: 277600622 X-Evolution-Source: pop://mailinglist%40farcite.net@mail.farcite.net/ Mime-Version: 1.0 X-Evolution: 00000746-0000 >I have seen RAM in the 16C54 that toggles on its own accord. I had an RCA Video Game (that console built around an 1802 micro in the 1970's) that had a spectacular display of memory problems. It had an "etch a sketch" type game where you could draw on the screen. By drawing a certain combination of lines when the cursor was on a particular cell you had about 6 blinking cursors on the screen. It required certain adjacent cells to be in a 0 state, and others to be in a 1 state for this to occur. I am a little surprised at all the discussion this particular failure has produced. Chips do fail. They have an MTBF figure. It may have even got an ESD zap without anyone realising during assembly/programming handling, which will often not produce a failure at the time, but some time (often months) later. It is just that chips these days are so reliable that we don't expect failures. -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.