From PICLIST@MITVMA.MIT.EDU Thu Nov 14 17:00:49 2002 Received: from cherry.ease.lsoft.com [209.119.0.109] by dpmail10.doteasy.com with ESMTP (SMTPD32-7.13) id A74111AC0084; Thu, 14 Nov 2002 17:00:49 -0800 Received: from PEAR.EASE.LSOFT.COM (209.119.0.19) by cherry.ease.lsoft.com (LSMTP for Digital Unix v1.1b) with SMTP id <13.007DA12E@cherry.ease.lsoft.com>; Thu, 14 Nov 2002 19:16:52 -0500 Received: from MITVMA.MIT.EDU by MITVMA.MIT.EDU (LISTSERV-TCP/IP release 1.8d) with spool id 4733 for PICLIST@MITVMA.MIT.EDU; Thu, 14 Nov 2002 19:16:38 -0500 Received: from MITVMA (NJE origin SMTP@MITVMA) by MITVMA.MIT.EDU (LMail V1.2d/1.8d) with BSMTP id 5862; Thu, 14 Nov 2002 19:16:13 -0500 Received: from tomts23-srv.bellnexxia.net [209.226.175.185] by mitvma.mit.edu (IBM VM SMTP Level 320) via TCP with SMTP ; Thu, 14 Nov 2002 19:16:12 EST X-Comment: mitvma.mit.edu: Mail was sent by tomts23-srv.bellnexxia.net Received: from amd1200 ([64.231.204.235]) by tomts23-srv.bellnexxia.net (InterMail vM.5.01.04.19 201-253-122-122-119-20020516) with SMTP id <20021115001612.QLHK9028.tomts23-srv.bellnexxia.net@amd1200> for ; Thu, 14 Nov 2002 19:16:12 -0500 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook IMO, Build 9.0.2416 (9.0.2910.0) X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 Importance: Normal Message-ID: Date: Thu, 14 Nov 2002 19:16:09 -0500 Reply-To: pic microcontroller discussion list Sender: pic microcontroller discussion list From: Herbert Graf Subject: Re: [PIC}:Project Idea To: PICLIST@MITVMA.MIT.EDU In-Reply-To: <04D03E2DF8BDBA4A8439617C9FFF092308E027@crystal-ex.crystalengineering.net> X-RCPT-TO: Status: R X-UIDL: 277600547 X-Evolution-Source: pop://mailinglist%40farcite.net@mail.farcite.net/ X-Evolution: 00000706-0000 > ...and the reason for that is that the old BIOS POST codes you remember > got dumped to the ISA bus, not PCI. They were quite easy to decode-- a > couple of octal latches, some 7-segment LEDs, and a fifty-dollar markup > are what I remember being typical. A handful of modern motherboards > have some surface-mount LEDs near the chipset to dump out POST > progress. > > The problem dumping data to PCI, if memory serves-- and it may not-- is > that you need to have a target vendorID:productID to send the > information onto the bus; ISA was more of a "broadcast" idea (you can > actually switch the traffic on PCI, though this only happens on MBs with > lots of slots or extra bridges). > > If you CAN build a product like you describe, it's a great idea, and the > best way to figure out if it's going to work is probably going to be to > get a PCI bus-traffic analyzer and see what you get when you boot up. In all boards I've seen the post code info is "broadcast" to IO address 80 the same as ISA. I actually built a PCI based post card for work this past year, used CPLDs (a PIC would be too slow alone), worked quite well. TTYL -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics