From PICLIST@MITVMA.MIT.EDU Thu Nov 14 06:14:11 2002 Received: from cherry.ease.lsoft.com [209.119.0.109] by dpmail10.doteasy.com with ESMTP (SMTPD32-7.13) id AFB310D10078; Thu, 14 Nov 2002 06:14:11 -0800 Received: from PEAR.EASE.LSOFT.COM (209.119.0.19) by cherry.ease.lsoft.com (LSMTP for Digital Unix v1.1b) with SMTP id <20.007D52E4@cherry.ease.lsoft.com>; Thu, 14 Nov 2002 9:00:20 -0500 Received: from MITVMA.MIT.EDU by MITVMA.MIT.EDU (LISTSERV-TCP/IP release 1.8d) with spool id 3957 for PICLIST@MITVMA.MIT.EDU; Thu, 14 Nov 2002 08:52:12 -0500 Received: from MITVMA (NJE origin SMTP@MITVMA) by MITVMA.MIT.EDU (LMail V1.2d/1.8d) with BSMTP id 8345; Thu, 14 Nov 2002 08:51:09 -0500 Received: from simmts2-srv.bellnexxia.net [206.47.199.11] by mitvma.mit.edu (IBM VM SMTP Level 320) via TCP with SMTP ; Thu, 14 Nov 2002 08:51:08 EST X-Comment: mitvma.mit.edu: Mail was sent by simmts2-srv.bellnexxia.net Received: from gm ([156.34.176.102]) by simmts2-srv.bellnexxia.net (InterMail vM.5.01.04.19 201-253-122-122-119-20020516) with SMTP id <20021114135108.SJCJ2935.simmts2-srv.bellnexxia.net@gm> for ; Thu, 14 Nov 2002 08:51:08 -0500 References: <3DD33141.52D59C2A@3mtmp.com> <002601c28bdc$817cc920$b64aa40a@gm> <000601c28be1$c109c2a0$8698ab41@THSystem> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Message-ID: <00f601c28be4$9af447e0$b64aa40a@gm> Date: Thu, 14 Nov 2002 09:49:08 -0400 Reply-To: pic microcontroller discussion list Sender: pic microcontroller discussion list From: Ray Gallant Subject: [PIC]: Detecting SRAM and eeprom To: PICLIST@MITVMA.MIT.EDU X-RCPT-TO: Status: R X-UIDL: 277600454 X-Evolution-Source: pop://mailinglist%40farcite.net@mail.farcite.net/ X-Evolution: 000006ae-0000 This may or may not help. I've done designs where I had external eeprom. This memory held 4 configuration modes (3 user & 1 default). In my pic initialization routine, I view the last byte in this eeprom and look for AA. If AA is there I do nothing. If not, I write a default configuration as one of the 4 available configuration mode, then I write AA to the last byte location. This way, when the pic 1st wakes up, the code writes the defaults the eeprom. You could store your next available memory address similarly. Consider the max write cycles for your device. {slewrate} ----- Original Message ----- From: "Tony Harris" To: Sent: Thursday, November 14, 2002 9:28 AM Subject: [PIC]: Detecting SRAM and eeprom > Ok, > > I've been thinking about this for a few days now and am not sure how to do > it. > > Let's say I have a little thing built that logs data - it requires external > SRAM, and external eeprom (SRAM for temp storage, and eeprom for long term > of a givin block of data for later download). > > I need to be able to auto-detect how much SRAM is available (ie: 0, 16, 32, > 64Kx8bits, 1 or 2 chips) and how much eeprom (if any) is available (1 or 2 > chips). > > I really am not sure how to do this, so any suggestions would be most > appreciated. > > I'm just not suere where to start. I'm planning on using parallel ram, > address lines A0 - A15 (want expandibility ;), with 8 bit for data. > > So, to sum up - I need to see if there are any chips there, and if there > are, how much data can be stored. > > Thanks in advance! > > -Tony -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics