The F628 might be different, but I tried to use the 12C671's internal osc as
a serial clock at 9600 baud and ran into a peculiar jitter problem; fastest
that would work is 4800 with any reliability. Even then, wrote a "corrector"
to try to read the actual speed and compensate for it, by using the first
start bit sent to it to measure its internal clock against the host serial
source.

--Bob Axtell
EDTec LLC
1-888-801-1416


----- Original Message -----
From: "Kyrre Aalerud" <kreature@C2I.NET>
To: <PICLIST@MITVMA.MIT.EDU>
Sent: Friday, November 08, 2002 4:40 AM
Subject: Re: [PIC]: How is the stability of the 16F628's internaloscillator
?


> Hmm, maby...
>
> My routine is adjusted so that each bit is timed at exactly 104 cycles,
> regardless of if it is a high/low low/high low/low high/high transition
and
> also if it is send or recieve...  Thus I am very close to the 102.16 that
I
> need.
>
> I think this will be ok...  It would also give me a very needed extra two
> inputs.
>
>     Kyrre
>
>
> ----- Original Message -----
> From: "Alan B. Pearce" <A.B.Pearce@RL.AC.UK>
> To: <PICLIST@MITVMA.MIT.EDU>
> Sent: Friday, November 08, 2002 11:35 AM
> Subject: Re: [PIC]: How is the stability of the 16F628's
internaloscillator
> ?
>
>
> > >It seems to me that in worst case scenario (following the specs),
> > >I can get a minimum speed of 3.65 MHz. That would be equivialent
> > >of 9.33 % error or 9.73 us pr bit.  start-bit + 8bits = 9*9.73
> > >and that is 87.59 us. Since I do centered sampling I have a maximum
> > >of about 50 us to go on if I manage to resynch to the next start-bit.
> > >(My rx routine skips almost 50us so that it can regain some lost
> > >time if this should be the case...)
> >
> > Can you do some sort of background task to monitor the bit width? E.g.
> when
> > you do your routine to check the centre of the bit, start a routine that
> > times to the end of the bit time. If you got to say 12% more than the
time
> > where a transition should take place, then the next bit is the same
state
> (0
> > or 1) as the current bit, so ignore doing an adjustment. If there is a
> state
> > change between 8% and 12% say (where the bit transition is expected at
> 10%),
> > then you have a bit edge and can adjust your timer value to tweak the
> timing
> > to centre the bit transition to where it should be. If you adjust in
small
> > enough increments then a noise pulse within the check window will not
> throw
> > you wildly out, although it will adjust it slightly.
> >
> > --
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> >
> >
> >
>
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>

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