> What I have is a 4.194Mhz xtal, and I am using TMRO as the rollover
> interupt.  I also have a 1:64 prescaler assigned to TMR0, so if my
> calculations prove correct:
>
> 4.194MHz equates to a .953uS state clock
>
> the prescaler would then give a interupt every (256*64)*.953us
> or 15.597mS.
>
> So if my end goal was to have the main ISR execute every second,
> then an additional counter loaded with 64 should do the trick

That would give you 998ms

To get much closer, re-load the timer with a better divisor than the
default 256

4194000/4 = 1048500 instruction cycles / sec

Reload TMR0 with 250 and use a /2 pre-scaler. This will produce
1048500/250/2 = 2097 (h0831) IRQs/sec, ==> two RAM counters

Have a look here for timer-related issues

http://www.piclist.com/techref/microchip/time.htm

particularly "Timer Tutorial (incl prescalers)" which addresses
 reload jitter

Alternatively, use a crystal that has a value more suitable for hex
division, eg 4.1952MHz or 3.2768MHz

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