This is long, so if you do not wish to be involved in the Pic beginners Kit, you may wish to discard this. This is my general discussion document for where I see the PIC Beginners Kit heading as a project. There are further comments in paragraphs at the bottom on why I have made some these choices. This is not to say that any item here is a "done deal", but rather a way of getting all info into one place. I have included paragraph numbers to attempt to make it easier to discuss points. At times this starts to sound like a cop show on TV :) Some of the points need re-ordering into other paragraphs to properly sort items together, but hey, this was thrown together when I should have been doing something else :) Later paragraphs dealing with software are my attempt at a specification of what will be required. This does not necessarily mean that it will get done. This release to be known as version 1 Pic Beginners Kit Brief, released 5 Sept 2002. I include this so that as alterations occur, it is possible to track which version of the brief people refer to. 1. General Aims 1.1 Provide already built development environment for PIC Beginners. 1.2 Programmer and PC interface provided on board. This chip is referred to as iPIC (Interface PIC) within this brief. Chip used to be 16F877A or 18F452. 1.3 Two sockets for microprocessors using 16F877A or 18F452. Other processors using Microchips' "standard footprint" (Microchip term) may be accommodated at a later date. Processors will be referred to as "Target 1" and "Target 2" within this brief. 1.4 One USB and two serial interfaces available to communicate with external host PC(s). 1.5 Some minimal display hardware on board for programming exercises with peripherals, and for debug indicator use. 1.6 Some minimal digital input hardware to allow experimentation with programs. Examples as in following sub paragraphs. 1.6.1 Push button switches. Suggest four switches to allow up/down, reset, clock setting type experimentation. 1.6.2 Rotary encoder to allow experimenting with value/voltage adjust experiments. 1.7 Separate push button reset switches to be provided for Target 1 and Target 2. 1.8 Further access to I/O ports using virtual peripherals accessed from PC Interface. Virtual inputs to include reset functions for Target1 and Target2. 1.9 Some minimal analogue hardware to allow analogue experimentation. Op-amps to buffer analogue impedances into the ADC to be provided. These are to have sufficient protection resistors to prevent damage to the PIC from inadvertent over voltage being applied. Suggestions in following sub paragraphs. 1.9.1 LM35 type temperature sensor, or similar which has voltage output. 1.9.2 Standard potentiometer for manual analogue input. 1.9.3 LM3919 type bargraph for analogue voltage display connected to PWM output, or monitoring potentiometer. 1.10 External ICSP connector to be available to program "off board" PIC's. (Off Board processors to be referred to as "Target 3") 2. Interfaces 2.1 Primary interface for programmer (as delivered) to be USB COM port. 2.2 Programmer to be jumper settable to Serial 1 port as alternative at 19.2k baud. 2.3 Primary Interface for Target 1 processor to be Serial 1, switchable to USB or Serial 2. 2.4 Primary interface for Target 2 processor to be Serial 2, switchable to USB. 2.5 Digital display hardware to consist of bargraph display and 4 digit, 7 segment display. 2.5.1 Bargraph display to be 8 bars, using ULN2803 as driver, allowing open inputs without damage. It may be possible to utilise a full 10 bar display if spare drivers exist in another ULN2803 package, as it seems that 10 bars is the standard LED bar graph package. 2.5.2 Seven segment display arranged to require multiplexed digits. Four digits with decimal points, and possibly colon (for clock use) if available (See 9.3 possible candidate). Current Sink drivers to be ULN2803 type, digit source driver TBD. 2.6 Virtual digital monitoring to be handled by Parallel In - Serial Out shift registers, permanently attached to port bits on both Target 1 and Target 2 processor. Where necessary jumpers and/or protection resistors to be fitted to prevent problems within the shift registers on ports available for analogue use. 2.7 Virtual digital input to the target processors limited to 16 bits, jumperable to individual pins on either processor. 2.8 All virtual digital I/O shift registers accessed using SPI port on iPIC. This information is supplied to the host PC for display using program provided with hardware. Output SIPO register suggested as 74HC595 and monitor PISO registers suggested as 74HC573/4. 2.9 Programming port to be selectable under software from the host PC. High voltage programming to be supported using on board generator. 2.10 Power to be supplied from a "Wall Wart" supply, with rectifier and regulator circuitry allowing a wide range of AC or DC input sources. My default connector for this is a 2.5mm type as used by Microchip on the Picstart Plus and other items that they supply using the universal switchmode supply. 2.11 Breadboard area to be provided using "measles array" of solder pads on 0.1" centres. Area to cover all otherwise unused space on PCB. Pads to be provided on edge of PCB for DIN 41612 connector, or 40 pin IDC ribbon cable header. Neither type of connector supplied with kit. 2.12 Both target processors provided with pins for making connections to breadboard area, or off board connections. 3 Interface Processor 3.1 The iPIC to be a 16F877A, but it may be that an 18F452 would be a better choice. This could be left to the person writing the software, as the footprint of the two processors is the same. 3.2 The processor to have a bootloader to allow for easy update of the internal software. 3.3 The iPIC to communicate at a standard baud rate, irrespective of USB or serial connection. This may mean any example software provided for the target processors would need to be operated at the same baud rate as it would not be known if the target is to operate on the serial or USB interface, and the USB driver would need to be set to a known speed for the iPIC. 3.4 The iPIC to control the generation of high voltage for programming. The decision to use the internal PWM hardware to drive a boost circuit in the manner of the ICD1, or use an external boost regulator is yet to be made. If the internal PWM hardware is used, I suggest that it be made a closed loop system using an ADC channel to monitor the voltage and control the PWM. 3.5 The iPIC should software select the target to be programmed, rather than use hardware jumpers for selection. This will need to include switching the high voltage programming voltage to the selected target. 3.6 A PWM port should be used to provide a "virtual analogue source" for testing programs on a target processor. Connection to be by jumper wire. 3.7 At least one ADC to be available as a "virtual analogue monitor" for connection to target processor circuits. Connection to be by jumper wire. 3.8 The iPIC programming software will need to be able to handle 16F87x, 18Fxxx and 16F62x processors as a minimum design requirement. Once software is stable, addition of other processors can be considered as room in the internal ROM allows. 3.9 A software facility to copy software from Target 1 to Target 2, or from either Target 1 or Target 2 to the target 3 ICSP port be available. This is in addition to downloading from the host PC. 3.10 The iPIC be able to be a "virtual serial port" to any of the target processor ports, using the RB6 and RB7 programming pins on the target chips for bit bash serial I/O. This would only be available where the target is not in debug mode, and will require a protocol to allow multiple target information transfer to the host PC through the iPIC. 4. Target 1 Processor. 4.1 A socket is provided to take a 40 pin DIP version of a 16F877, 16F877A or 18F452. Consideration will need to be given to supporting later processor announcements by Microchip, as they seem to have used this pinout as a standard foot print, and refer to it as such in their literature. A programmed 16F877A to be provided already fitted in this position. 4.2 The "as shipped" kit to have the hardware I/O jumpered to suitable pins so the program in the chip will allow demonstration of the I/O functions of both hardware and virtual I/O without any operations being required on the board by the user. 4.3 The processor shipped to be loaded with program that exercises the hardware as connected when shipped. A copy of this program to be included on the software CD to allow the user to re-instate it if desired after overwriting it. Suggested experiments listed in following sub paragraphs. 4.3.1 Digital bar graph steps through bars, one bar at a time, or in "thermometer mode" to allow user to observe use of virtual I/O monitoring. Step rate variable to allow effect of I/O being faster than virtual I/O sample rate. 4.3.2 Use 7 segment display as counter. Count could be controlled by rotary encoder, or by internal timer. Again count rate variable to see effects on virtual monitor. 4.3.3 Use 7 segment display as clock. Use push buttons or virtual I/O for setting time and/or alarm. Again an exercise in virtual monitoring. 4.3.4 Use 7 segment display as voltmeter readout to read voltage from potentiometer and/or virtual analogue source on iPIC. Exercise in using virtual analogue monitor on iPIC as well. 4.3.5 Use temperature sensor chip as analogue source for voltmeter operation. Other wise very similar to 4.3.4. 4.3.6 Use "virtual comms port" on programming lines to get target processor to relay message out serial port from typing coming in through iPIC from host PC. 5. Target 2 Processor. 5.1 A socket is provided to take a 40 pin DIP chip of identical specification to any that can be fitted to target 1. No chip is supplied in the "as shipped" board. The chip fitted to this socket does not have to be identical to the chip in Target 1, it can be any chip from the allowable family. 5.2 The only dedicated hardware provided for this target is a jumper to allow the uart to be connected to the serial port. Leaving the jumper off allows the uart pins to be used as general I/O. 5.3 Connection pins are provided to allow any hardware peripheral on the board to be jumpered to this target using flying leads. No assumptions are made about pin usage other than possible uart use as given in 5.2. 6. Target 3 ICSP port. 6.1 A connector is to be provided to allow a PIC on an external PCB to be programmed using the on board hardware. It is yet to be decided if this should use an RJ11 connector in the same manner as the Microchip ICD. 6.2 The programming hardware is to be capable of using this port for debugging use in the same manner as the Microchip ICD. 6.3 No cable will be provided with the kit for this port. 7. PCB hardware. 7.1 The iPIC is to be soldered in circuit. My preference is to use a surface mount chip. If this is an 18F452, then this will have no impact on ordering as it will be a different processor to that supplied for target 1. I am not unmovable on this, the final decision resting with those who assemble the hardware. 7.2 The Target 1 and Target 2 processor sockets should have enough room around them on the PCB to use ZIF sockets if the price for these is suitable. 7.3 All components as far as possible should be surface mount. Again I am not unmoveable on this, but believe it would probably be easier for production machinery. Again the hardware manufacturer to have final say on this. 7.4 My favoured size for the PCB is 100mm x 160mm (Eurocard size), but to get a reasonable breadboard area may need to go to 100mm x 220mm (extended Eurocard) or 200mm x 160mm (double height Eurocard). Again I am not inflexible on this, but see it as a size that many in our business would use as the basis of developing prototypes. 8. Host PC Software. 8.1 Host software will need to be written to handle various functions as listed in the sub paragraphs below. 8.1.1 Download and control programming of target device from host. This includes selection of the target processor to be programmed. 8.1.2 Control and display of virtual I/O information. This includes remote reset of the target processors. 8.1.3 Conversion of virtual I/O data into human readable display on screen to form a virtual peripheral (e.g. converting port bit information into LCD display). This may also require setting which port pins, and in which order are to form the input to the virtual peripheral. 8.1.4 Allow up to two "dumb terminals" as separate windows within the host program to handle I/O from either serial ports, or "virtual serial I/O" handled through the iPIC as mentioned in 3.10. "Serial Ports" should include USB comms ports as an option. 8.1.5 Control the ICD functions in the iPIC to allow the user to debug programs. 8.2 Any virtual peripheral suitable for use in paragraph 8.1.3 should probably be written as a DLL (or *nix equivalent) to maximise the portability of code. A defined interface for writing such DLL code will need to be written to facilitate this. 8.3 The software should be written in a language that allows best portability to the widest range of systems practicable, with a minimum of effort. To me this means that an environment which allows programming isolation of display handling from coding requirements would be best. Use of Delphi/Kylix or a multi-platform C/C++ would seem to be the most sensible way. A *nix port can probably be ported to a Mac OS environment with minimum extra effort due to it's *nix basis. 8.4 A suite of assembler, linker, and debugger functions which link to the source code will need to be provided. Thought will also be needed in what to provide as an editor. 9. Chip selection to use on the PCB. 9.1 This is my selection of hardware to use on the target PCB. It is not set in stone, just what I have figured would be useful items to use. 9.2 Bar graph display. There are a wide range of these available in 0.3" DIP packages. I am not aware of any surface mount versions, but pointers to low profile ones may be nice. 9.3 Seven segment display. There are two possibilities I like. The first is an Agilent one, which appears to be a new device that the Agilent search engine cannot find on their site, but is listed in the seven segment display list. Agilent #HDSM-560G, 0.39" 4 digit green display. The first digit is actually a starburst allowing +, -, / etc, and it also has a colon between the two centre digits as well as a decimal point for each digit. Cost unknown. The second is a Kingbright LC-305MK, stocked by RS Components, but no longer on the Kingbright web site. This means it is probably a "Not for New Design" type device. Five digit 7 segment with DP for all digits, plus DP's at the top of each side of the centre digit, allowing a (wide spaced) colon for clock use, or two DP for inverted use. 9.4 Analogue input device, my suggestion being a temperature sensor such as an LM35, to represent a potential "real world" sensor that the user can experiment with. LM35 comes from National Semiconductor, but other chips with voltage output are available. 9.5 Analogue output device, my suggestion is an LM3919 bar graph display driver. This can be jumpered to show a single bar or "thermometer" type display. Useful for displaying filtered PWM output. 9.6 High current driver, ULN2803A, surface mount version, available from Toshiba and Allegro. Eight drivers in one package, for driving 7 segment display and digital bar graph, also used for miscellaneous drivers like programming high voltage switch, and virtual reset buttons. Useful as it has internal resistors in series with the base to limit current, and base to ground to put into known state if user leaves unconnected. Being bipolar, not damaged if input O/C. 9.7 Op-amps to buffer/protect analogue i/o. Suggest National Semiconductor LMC6482/4 which is a dual/quad rail to rail I/O device. Works down to 3V, so ideal to run off 5V processor supply. Actual device used depends on how many individual op-amps we require. 9.8 Virtual Output - because of the number of I/O lines we would be wanting to monitor, I believe we would need to use a shift register to get them all into the iPIC to transfer to the host. I suggest using a 74HC573 or 74HC574 8 bit latch/shift register for this, depending on wether an edge latched or fall through latch is perceived as more desirable. These would require an extra line on the iPIC to drive the latch function, but with all bits latched at once, it would provide a "window" on the state of the processors. I count 33 I/O lines, plus reset to monitor, so 9 shift registers would monitor both processors, and have a handful of pins left over that the user can connect elsewhere using floating leads. 9.9 Virtual Input - I am looking to use a pair of 74HC595 SIPO 8 bit registers to give 16 output lines that can be connected to processor pins on either processor using flying leads. A small (100 ohm?) resistor would need to be connected in series with each output to protect things if connected to a PIC pin configured as an output. Like the HC573/4, these would need another separate pin to drive the latch line. 9.10 Pull up/down resistors. Suitable resistor packs to be sourced. Not sure if I should just go with SIP through hole packs or find SMD packs. Well that will do for today - i will come back in the morning to a wealth of discussion points I'm sure. I believe my spell checker caught most of the errors, but don't count on it :) -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics