I am trying to interface an ADC0831 to the PIC18 because: 1. The PIC's analog inputs cannot handle the high impedance of the source signal. 2. I have several ADC0831's lying around - I need a quick solution, and don't have time to order more parts. The problem: Using the SSP interface, I find that the results are correct - *to an extent.* Values are scaled properly, but they are always between 128 and 189 - not 0 and 255. Vin- is at 0V, and Vref is at 5V. The analog signal is also 0-5 VDC. SSP settings are as follows: SSPSTAT = 0xC0 SSPCON1 = 0x32 SSPCON2 = 0x00 Or, Input data sampled at end of output time Data transmitted on rising edge of clock [given these two settings, data received on falling edge, correct?] SSP enabled Idle state for clock is low SPI master mode, clock Fosc/64 Fosc = 5 MHz, thus the clock is roughly 78 KHz (well within the 10-400 KHz range of the ADC) Code is as simple as possible: #define ADC_CS PORTB,0 ;chip select pin on ADC0831 ;NOTE to PIClist readers: ;this pin is not configured as output, ;not interrupt ;also, RC3 (SCK) is output, RC4 input (SDI) ;operation verified on scope GET_SSPCOM BCF ADC_CS ;hold ADC0831 chip select low MOVLW 0xA0 ;move dummy data to SSPBUF to start reception MOVWF SSPBUF SSP_ACQ BTFSS SSPSTAT,BF ;if data has not yet been received GOTO SSP_ACQ ;keep checking (wait for data) MOVFF SSPBUF,ADRESH ;move received data to command register ;NOTE to PIClist readers: ;ADRESH is NOT being overwritten ;the value is placed here to make the transition ;to an external ADC as smooth as possible ;without altering the rest of the module ;[in standard cases - 999 of 1000, the on-chip ;ADC would work fine] ;Changing the destination register ;did not affect processing CALL ADRES_DISP ;TEST - display value received ;Note to PIClist readers: ;simple, tried & tested LCD routine ;not the cause of problems - removing this call ;did not affect performance - digital output ;on PORTD (the 'real' result) unaffected BSF ADC_CS ;chip select high once data received GOTO PROC_AD ;continue processing My first assumption was that the first two bits are always read as '10', leaving a range of 128-191. Upon reading the ADC datasheet more carefully, I noticed that the ADC does not begin shifting out until the falling edge of the SECOND clock, so I tried adding one more precisely timed clock pulse (ensuring that it fell between the 40-60% duty cycle limitations: +/- 1 instruction cycle), then placing data in SSPBUF so that the read would start on the second pulse. No change. I also tried adding delays so that CS is held low for a longer period of time (14.4 us) before and after communication. No change. I have found countless examples of using the ADC with a BASIC stamp, but the only PIC/asm example I could find is in "PIC'n Up the Pace" - a great book - if only I had it. I would gladly buy it if I could have it *right now*, but since I'd have to wait until at least Monday for it to arrive, that's not an option. Has anyone else had success with this configuration? Am I perhaps making an invalid assumption or overlooking something simple? Any help is greatly appreciated! Jen -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! email listserv@mitvma.mit.edu with SET PICList DIGEST in the body