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> > > Now, see, if *I* were designing a processor, a reset (i.e.
> > > external or reset instruction) would clear the entire contents
> > > of memory.
>
> Luckily you don't, for this would kill some interesting
> applications, like the reset-pin interface (chip measures the time
> between reset, uses it as data input from user or maybe for
> bootloading or the like)

Ok, fair enough on that one.  I've never heard of it being used
before, but fair enough.

> and the
> watchdog-temperature sensor (measure watchdog timeout to determine
> die temperature).

I can't even see how that's related.  I said in that post that most
of the existing "resets" used by Microchip were, in fact, just
interrupts that cleared the PCL.  I've always though that the
watchdog reset, should be considered the interrupt that it is, if you
want to use it as a reset, add a GOTO H'00' and you've got yourself a
"reset".

Walter Banks has mentioned a post crash dump as a useful debudding
tool.  That's fair enough, except that that can be handled by an
interrupt.

Let me play devil's advocate for a moment.

<devil's advocate>
I'm not arguing about convention, here.  I'm sure you're right on
that count.  I did say that if *I* were designing a processor, that's
what I'd do.  I see 4 real classes of processor break.

1) interrupt--  Processor goes to an interrupt handling routine.
Returns to code it was at upon completion.
2) partial reset-- (what Microchip calls a reset) PCL is returned to
0.  Stack contents are invalidated, if not deleted
3) full reset-- Processor is returned to its power on state.  RAM is
cleared.  all non-fused config is reset
4) power cycle-- Power to processot is removed and restored

There was a thread earlier about processor design, with respect to
the PICList having a special PICList processor built for us, which I
think is a great idea.

Since this all goes back to my statement "if *I* were designing a
processor" I guess I'm going to have to clarify more.

If I were designing a processor, there would be the full reset
conditions that I mentioned, and on top of that, there would be
prioritized interrupts (probably about 4, 8 or 16 levels), the
highest of which would be initiated without a question of GIE.  I
would make several external pins mapable to interrupts (of various
priorities)/normal I/O.  There would be one full-reset pin.  One that
basically erased all volatile RAM on the processor.  You can't get
more of a clean start than that.
</devil's advocate>

Now, I hope you can see that there are other functional schemes that
could use a full RAM clear in the reset process.  I don't think
there'd be much loss there, but there might be very little gain.
I'll leave that analysis to the professional chip designers.

- --Brendan
- ---
"Rejection out of hand of all but one's favoured alternative may cost
you dearly in one way or another." -Russell McMahon

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