Er....

My last response is STILL not right....

bit FSR0,7 is not implemented and always reads as zero.

So, the test condition at the end of the loop has to be:

TSTFSZ    FSR0H

Now, I think that is finally right.

Bob Ammerman
RAm Systems





----- Original Message -----
From: "Scott Dattalo" <scott@DATTALO.COM>
To: <PICLIST@MITVMA.MIT.EDU>
Sent: Monday, August 19, 2002 3:35 PM
Subject: Re: [PIC]: Challenge: 18F Clear RAM


> On Mon, 19 Aug 2002, Bob Ammerman wrote:
>
> > Short:
> >
> > clrf    FSR0L
> > clrf    FSR0H
> >
> > (or LFSR 0,0)
> >
> > loop:
> > clrf    POSTINC0
> > btfsc  FSR0H,3
> > bra    loop
>
> I think you meant btfss instead of btfsc. If so, won't that just get 0x000
> - 0x3ff? You can't change the 3 to a 4 or you'll wipe out the SFRs between
> 0xf80 - 0xfff (including POSTINC0 which will cause an infinite loop).
>
> hint, suppose you use LFSR 0,0xf7f?
>
> Scott
>
> --
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>

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