-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 What no one has mentioned (surprisingly) is that you have to be careful with the bus width. For example, hooking up an old EPROM to a PC bus. Old EPROMS are, in general, 8-bit devices. Modern (PC) CPUs are, in general, 32-bit devices (except for the 64-bit parts that are still under the final stages of development, and the ancient 16-bit devices). This gives you 2 options: 1) use tie the remaining bits beyond those used by the EPROM low, when the address is valid, and 2) use 4 ganged EPROMS all with the same enable circuit. Well, you could probably work out some other options, but those are the simplest, by far. How were you planning to implement this? Old ISA bus? PCI bus? If either of those, you don't need to worry too much about the PC bus structure, but instead about the spec for the particular bus that you'll use. If, on the other hand, you're simply interested in learning about busses, here's what I know of them (though I'm probably just reiterating what's been said): Busses are, in general, parallel in format. They are composed of two seperate busses, the address bus, and the data bus, which are sometimes multiplexed by the use of control lines (ALE(adress latch enable) WR(write) RD(read) are the common control lines). If the busses are not multiplexed, the WR and RD lines are still needed, but the ALE can be implied. There is no clock, in general, instead, everything is controlled by the edges of the WR, RD, and ALE lines. If you're attaching a device to the address bus, a multiplexer IC and some inverters can be used as an easy way to decode the address bus into an enable signal for the target device. A multiplexer can be used as a sort of a boolean function generator. If you want more info on that, it's probably somewhere on the web, but if you can't find it, ask me, or the list. In this way, busses are actually pretty simple in concept. The process is pretty much as follows for at least one kind of multiplexed bus 1) address goes on bus 2)ALE signals address is valid 3)the target device reads the address 4)the address is removed from the bus on the opposite edge of ALE 5)WR or RD indicates which device writes to the bus (WR and RD can be combined into a single signal through use of the ALE edge, but this can be somewhat more complex) 6)The data appears on the bus 7)on the opposite edge of WR and RD, the data is read by the appropriate device, and removed from the bus I think that pretty much covers one scheme for bus interfacing, though there are several. There are likely many good books and much online information available regarding bus type devices. I suggest looking into other information sources if you want to know more. Feel free to correct me, anyone, though I think I've got things pretty accurate here. Regards, - --Brendan -----BEGIN PGP SIGNATURE----- Version: PGPfreeware 6.5.8 for non-commercial use iQA/AwUBPWEqxQVk8xtQuK+BEQIqAACgv+a9nDJuheh3XaSTMzK4y5Ik/p4An3BW zWwsh2XFRyNA4S1Dz4sXBm0B =9t6m -----END PGP SIGNATURE----- -- http://www.piclist.com hint: To leave the PICList mailto:piclist-unsubscribe-request@mitvma.mit.edu