On Sun, Aug 18, 2002 at 08:43:26AM -0400, Jason Harper wrote:
> BAJ wrote:
>
> > But you're defining a behavior that's not going to have major relavence
> in
> > the vast majority of project development.
>
> Displaying output and supplying input doesn't have major relevance to most
> projects?

You must have missed the context. I was specifically and only referring to the
logic analyzer function, whose job isn't either displaying output or
supplying input.

>
> > How many of us use logic analyzers on a daily basis?
>
> Not many, of course.  That's because most of us don't HAVE a logic analyzer
> to use on a daily basis!

It's interesting that we're on agreement with that assesment.

>
> I'm trying to come up with a system that is an improvement over existing
> development techniques, for users of all experience levels.  You seem to
> want to drag it down to something that offers nothing over existing
> programmers.

Are you sure that you're talking to me? Or was that directed to Roman? ;-)

We have the same aspirations.

>  Go buy a cheap Tait-style programmer and glue a PIC in the
> socket, that appears to fully meet your requirements.

Not even close:

* It still has a programmer.
* It doesn't have the right interface.
* It doesn't have any I/O interfaces onboard
* It doesn't have a prototyping area.
* It would still require transfer of the chip from the programmer to the target.

It's 0 for 5 in my book.

Jason, I'm simply trying to apply Occam's Razor to the problem at hand. You're
proposing a 2 chip system against my 1 chip system for a task. Your proposal
adds more development and usage complexity. It also adds more potential failure
points. In my esitmation there needs to be a significant daily benefit to
offset that additional complexity. All I'm asking for is a clear definition
of those benefits. So far you've given 3:

* Full I/O use
* Full memory use
* Logic Analyzer

Now given the fact that both design proposals includes alternative programming
ports, the first two become a wash.

So all that's left is the LA. I see both implementation and usage issues:

* Insufficient sample rate
* Problems with storage of samples
* Hardware triggers
* What's the display mechanism going to be?

Usagewise it just adds a more complex component to the process.

Just some thoughts.

BAJ

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