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> > Yowza!! 100 slaves?  Well, I can give you one recommendation
> > right away.  IIRC the maximum recommended bus length is 10cm.
>
> Recommended in a particular situation perhaps, but IIC has no
> official maximum bus length.  The hard limits are the maximum
> capacitance (400pF if recall), and the maximum sink current
> required to lower a bus line to logic 0 (around 3mA, again from
> memory).  These parameters and the maximum clock rate will dictate
> the maximum bus length in your case.  Note that you get to chose
> the clock rate.

400pF sounds right to me.  I still don't think that suggesting a hub
IC is a bad idea.  It might make things considerably simpler.
Especially since it has select lines, which would enable it to have
up to 4 devices with the same address in the circuit (5 port hub, 1
port goes to master, therefore, only 4 devices with the same address
can be used.) so long the enable lines were used well.

Bus length and clock speed are, of course, the determining factors.
I expect that the 10cm guideline was placed there as a rule of thumb
for what is likely to be about 400pF.  Track placement matters, of
course, etc. etc. etc.

Note on track placement: IIRC the recommended track placement for
longer runs was this: Vcc SCL GND SDA or something like that.

- --Brendan

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