William Hubbard <kwooda@NETZERO.NET> wrote:
> What is happening is that when the low byte of the counter rolls over
> (incrementing the high byte), it appears that sometimes the CCPR1H register
> has the value of TMR1H before the roll-over, and CCPR1L has the TMR1L value
> after the rollover (i.e. the capture is not correctly recording the timer 1
> values), ...

I've never encountered a the particular problem myself, but after perusing
the data sheets, errata, manuals and AN594, this sounds like a silicon
design bug. I would guess that the transfer to the capture register happens
on the same internal clock edge as the carry from TMR1L to TMR1H, creating
a "race condition" between the two events.

Have you tried this on more than one chip, and do all chips exhibit the
problem to the same degree?

> Is there a way I can use a capacitor or something to delay the trigger
> signal ever so slightly to see if this makes any difference?

I doubt it. The edge on the pin is probably synchronized to the PIC's
internal clock before being applied to the CCP transfer logic.

Another possible explanation would be metastability in the synchronizer
itself; in this case, adding a slight delay would have a huge effect on the
problem. Try an R-C time constant of 10 ns or so (e.g., 100 ohm resistor
and 100 pF capacitor). Connect the resistor between the source and the CCP
input, and connect the capacitor between the CCP input and ground.

Let us know what you discover.

-- Dave Tweed

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