>>By the way, I don't have a spare pin to implement hardware solution. All
the
>>detection and mitigation must be done in software.
>>
>>My question is, how to do it?
>
>If you set the input pin to output, drive it low and then read it, you can
>tell if it is *really* stuck to Vdd, as the PIC reads the actual pin state
>rather than the output latch. You might have to beef up your
>external drive circuit to guarantee it has more drive than the internal
>n-channel transistor.
>
>Connecting a small capacitor on the pin might allow you to get an idea
>that is more accurate (drive it low, then wait- with a time-out- for the
>pin to come high with your external pullup (open-drain or collector drive).
>If the pin fails to come high, or comes high TOO fast, then you have
>a problem. Don't make the time constants more fussy than you have to,
>the thresholds vary on the inputs etc. Homework.

Also have a series resistor from the external circuit to the pin. This will
serve three purposes.

1. It protects the pin from ESD damage or other damaging transients coming
from the external circuitry. To maximise the protection I would put the
resistor as close to the processor pin as practical to reduce static and EMC
pickup, but this is a personal preference.

2. It gives a time constant for the capacitor charge mentioned in the quoted
piece above.

3. It means that when you change the pin to output mode, the output has an
impedance to drive which will allow the pin to change state so you can see
that state change during your test. If the impedance is too low then the
output driver will get damaged by attempting to supply too much current, and
damage the processor chip, rather defeating the test :) I would be looking
at using a resistor in the 100 ohm to 1k range, but possibly going higher to
help item (2). However you do not want to go too high, else you will get
problems of the type mentioned in item (1).

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