> > that mean an EEPROM > 1k x 8 can't be accessed above
> > 03FF ?
>
> No, different address space.

I realised my mistake of misreading the contents of the control
byte which comes after the start bit. It depends on which memory
chip you're using, eg 24C32 or eg 24AA174. My fault for giving
myself a little scare by reading too much. But a little adrenaline is
a great focussing aid ;-)

> The 7 or 10 bit address refers to the addresses of slave modules
> on the IIC bus.  This has nothing at all to do with the EEPROM's

Until I pick up the AMD 64k device I'm testing code on an Atmel
24C32 (8k). This, as you say, has 1010 + xxx + R/W after the start
bit, then the address bytes. The 256 and 512 devices also do it
this way so the C32 code should work OK

> internal address space.  By the way, almost everyone uses 7 bit
> addressing.  127 possible slaves is usually WAAAAAYYYY more
> than enough.

I would expect you'd have problems with signal quality, although if
the device is in power-down mode after an operation maybe the
SDA and SCL pins in turn do not present as high a load on the bus
as when the chip is active. It doesn't say in any of the datasheets
one way or another AFAICT

> Also, most EEPROM chips only use 7 bit addressing, and often have
> most of those hard wired.  Usually you only get to chose the low 1 or 2
> address bits the chip will respond to.

The 8-pin memory chips all seem to have A0 A1 and A2 (8 chips per
bus, 000 to 111) available for hard wiring, whereas ICs like the PCF2116
or PCF8583 have just A0

> Yes, that means you can't put more than 2 or 4 of these chips on the
> same IIC bus without some external selection scheme

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