-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 As promised, here's the guide. I hope it helps, and doesn't contain too many glaring omissions or errors. I suspect Olin will at least be able to comment on the validity of this info. All it really is, is condensed info from he datasheet, but the datasheet has info in it that's just not necessary for someone who just wants to get the interface up. - --Brendan - ---------------------------------------------------------------------- - ----------- [General] There are 6 registers used in I2C operation: SSPCON SSPCON2 SSPSTAT SSPBUF SSPSR (not directly accessible) SSPADD [Initialization] To initialize the I2C module, follow these steps information in "()"s explains the use of various segments. Set SDA to input Set SCL to input (For 100kHz/1MHz operation) Set SMP (For 400kHz operation) Clear SMP (For Standard I2C operation) Clear CKE (For SMBus operation) Set CKE Set SSPEN Configure SSPM3:SSPM0 (SSPM3:SSPM0: Synchronous Serial Port Mode Select bits) (0000 = SPI Master mode, clock = FOSC/4) (0001 = SPI Master mode, clock = FOSC/16) (0010 = SPI Master mode, clock = FOSC/64) (0011 = SPI Master mode, clock = TMR2 output/2) (0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.) (0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled.) SS can be used as I/O pin.) (0110 = I2C Slave mode, 7-bit address) (0111 = I2C Slave mode, 10-bit address) (1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))) (1011 = I2C Firmware Controlled Master mode (slave idle)) (1110 = I2C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts enabled) (1111 = I2C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts enabled) (1001, 1010, 1100, 1101 = Reserved) Done! Review the datasheet for additional information, and for register addresses. [Use of the I2C interface] You'll have 6 functions for I2C, once the port ins initialized. They are: Start Repeated Start (that's start when there's already been a start, but no stop) Send Stop Set receive Acknowledge a received byte I assume that these are implemented in software, not hardware, though *I* think that a start an Ack should be automatic. - From the datasheet, >A typical transmit sequence would go as follows: >a) User generates a START condition by setting >the START enable bit (SEN) in SSPCON2. >b) SSPIF is set. The module will wait the required >start time before any other operation takes place. >c) User loads SSPBUF with address to transmit. >d) Address is shifted out the SDA pin until all 8 bits >are transmitted. >e) MSSP module shifts in the ACK bit from the >slave device and writes its value into the >SSPCON2 register (SSPCON2<6>). >f) MSSP module generates an interrupt at the end >of the ninth clock cycle by setting SSPIF. >g) User loads SSPBUF with eight bits of data. >h) DATA is shifted out the SDA pin until all 8 bits are >transmitted. >i) MSSP module shifts in the ACK bit from the >slave device, and writes its value into the >SSPCON2 register (SSPCON2<6>). >j) MSSP module generates an interrupt at the end >of the ninth clock cycle by setting the SSPIF bit. >k) User generates a STOP condition by setting the >STOP enable bit, PEN, in SSPCON2. >l) Interrupt is generated once the STOP condition >is complete. - From the looks of things, it's a pretty SSPIFy systems ;) The CPU needs to check the S and P bits before any attempt to take control of the I2C bus. If P is set, then it can proceed, if not, it must wait for P to be set, and can be interrupted when it is. Start should consist of: - -- Set SEN (SSPCON2<0>) - -- S (SSPSTAT<3>) is set, and, when SEN is automatically cleared, the start condition is complete, and a SSPIF interrupt occurs to handle the data write. If the bus is in use when the start function is called, the BCLIF interrupt flag will be set. A data write can occur before the start condition is complete, but will not be sent because queuing is not allowed. WCOL is set to indicate that the data has not been transmitted. When a start is detected on the bus, the S bit is set. Repeated Start - -- Set RSEN (SSPCON2<1>) - -- Similar to Start Send - -- Load SSPBUF with the data to send. - -- The BF flag will be set, indicating that the buffer is full until the transmission is complete, at which point an interrupt will occur (SSPIF). If a write to SSPBUF is attempted while a shift is in progress, WCOL is set, and the buffer is unchanged. If the is an acknowledge, the ack bit in SSPCON2<6> will be clear. If not, it will be set. Stop - -- set PEN (SSPCON2<2>) - -- When a stop is complete, the P bit (SSPSTAT<4>) is set. Also, when a stop is detected on the bus, the P bit is set. Recv - -- set RCEN (SSPCON2<3>) - -- When the SSPSR receive buffer is full, the BF flag is set, and there is a SSPIF interrupt. The BF flag is cleared automatically when the CPU reads SSPSR. The SSPOV status flag is set when a receive occurs while the BF flag is already set. If the user writes to SSPBUF while a receive is in progress, WCOL is set, and SSPBUF is unchanged. An Ack can be set after a receive is complete. Acknowledge - -- Set ACKDT Set ACKEN (SSPCON2<4>) - -- If an ack is desired, set ACKDT if an ack is not desired, clear ACKDT. Either way, Ack should be used after a receive has occurred. As usual, any write to SSPBUF while an Ack is in progress will cause WCOL to be set, and SSPBUF will remain unchanged. Once the Ack process is complete, ACKEN will be cleared automatically. -----BEGIN PGP SIGNATURE----- Version: PGPfreeware 6.5.8 for non-commercial use iQA/AwUBPUrcvQVk8xtQuK+BEQJ5IACeP0Sx+ETQfw7pQrq1daeoH9hfHSAAnAkI Af07hpkKCzK5plTOE17Hted3 =JMhD -----END PGP SIGNATURE----- -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.