> I'm reasonably comfortable with I2C, it's simply Ignorance of the > 16F877's I2C module that's today's headache OK, then here are some points about the MSSP module that you want to think about up front: 1 - There is a bug in master mode. The ACK bit from the slave is sampled on the falling edge of SCL instead of the rising edge. This causes a race condition between SCL falling and SDA being released from ACK. Even though the master is controlling the clock, its internal circuitry looks at the actual bus level to react to SCL. If the slave threshold for a 1 on SCL is higher than that of the master's, then the slave sees the falling SCL edge before the master. This can cause the slave to release the SDA line from ACK before the master samples SDA to read the ACK bit. The result is that the slave wrote ACK, but the master reads NACK. This may sound like a rather unlikely scenario, but I have seen it happen. That's how I found this bug in the first place. Consider the effect of slightly more stray capacitance on the SCL line than SDA, and you can start to believe it might be possible. My workaround is to use the minimum pullup resistors for both lines, then add about 100pF to the SDA line. That delays SDA rising edges enough to get past the short race condition. In practice I've seen 47pF always work, although something like 36pF (don't remember exactly) worked most of the time but not always. 2 - Note that a slave in clock stretch mode holds SDA according to the high bit of SSPBUF. When the SSPCON,CKP is set to release clock stretch, clock is released immediately. While this makes sense, the fix to #1 can cause trouble here at high CPU clock speeds (has nothing to do with IIC clock speed). The fix for #1 slows down SDA a little with respect to SCL. With a 20MHz slave, one instruction is not enough time to start driving SDA appropriately before clock is released. This can cause the high bit of the data byte to be read as 0 by the master when it 1 inside the slave. The fix is to set SSPBUF a few instructions before setting SSPCON,CKP. Insert a few NOPs if necessary. 3 - The MSSP module does not directly support slave flow control during a write. The master can always slow down communications to avoid being overrun of underrun because it controls the clock. A slave during a read sequence can (automatically does) do clock stretch to avoid underrun. However, there is nothing a slave can do to avoid overrun during a write, at least not directly using just the IIC bus via the MSSP. 4 - The SSPADD register in slave mode holds the slave address shifted left one bit. This makes sense because that is how the address is aligned in the address byte, but the docs don't come right out and tell you that. ***************************************************************** Embed Inc, embedded system specialists in Littleton Massachusetts (978) 742-9014, http://www.embedinc.com -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.