Thanks Roman. Yes, you are once again correct in the combination of factors
statement.
I would like to gate the devices for a longer period, but hardware now
limits the design to two choices. One is the 3 uS pulse, which admittedly is
a bit short, but has always worked reliably until this application. I can
also use an output that will continue through the end of the 1/2 cycle. This
choice will require a MUCH LARGER resistor to handle the power at the
increased duty cycle.

Since last *talking* I have found an RC gate snubber on each phase that is
in effect delaying the current to the gate. Three time constants here is
enough to nearly negate the gate pulse in this case. I will next remove
these and build snubbers between anode and cathode. Again, these will have
to be much larger than the gate snubber, but it is a common practice to
mount the large oil filled caps off-board, so it shouldn't even look so bad.

Finally, a knowledgeable sales engineer (finally) pointed to the internal
resistance between gate and anode as another factor in determining gate
current. This in effect creates a voltage divider for the gate signal making
the current even smaller.

Since this ap is way above the latching and holding currents at the lowest
command levels, I think it's time to hit the gates harder. I can even put a
small RC network in parallel with the existing gate resistors to make a
snappier pulse as the cap charges and discharges.

Of course, I'll try one at a time.

The PIC puts an 8 bit command value on a bus that is used to tell separate
hardware when to fire. That hardware is clocked by a PIC pin that is used to
generate 256 clocks between 1/2 waves. As such, even though the PIC
generated clock is at 32kHz, the hardware it gates has only a 3.2uS high on
it's output pulse.

I think it all needs to be done on the PIC  - next time around....

CL

> You may have combination of factors. What is the
> minimum load? Do you have enough holding (through)
> current at the low conduction angles? If using PIC
> gate drive and optocouplers why only use a very
> short gate pulse? The pulse may occur at a point
> corresponding with a mains voltage anomaly (spike,
> lag etc) where the holding current may not be enough
> espcially at low angles which are lower anode currents.
>
> It would be better to keep gate voltage within the
> proper levels, and a nice constant voltage, and use
> a full-length PIC pulse from the start of conduction
> to the end of the half-cycle.
> -Roman
>
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