On Mon, 8 Jul 2002, Thomas C. Sefranek wrote:

>On 8 Jul 2002 at 0:36, Peter L. Peres wrote:
>
>> On Sun, 7 Jul 2002, Thomas C. Sefranek wrote:
>
>> >Considering the large GS capacitance, I'd guess most circuits would form an
>> >integrator.
>>
>> GS capacitance ~= GD capacitance on many MOSFETs. If you do not control
>> the gate firmly in both directions then you are likely going to have
>> surprises. If you scope the gate on a switching FET you can see the
>> changeover points very clearly. Not only is Cgd large but it changes with
>> the applied D voltage.
>
>I do see the miller effects on the gate voltage.
>>
>> >(Tiny spikes make NO difference, nor do they puncture the gate.)
>>
>> My experience with tiny spikes is, that they can breakdown the gates just
>> fine, at least on FETs <= 100A, or cause invisible failures that doom the
>> device later. Maybe yours have integral gate protection diodes.
>
>Since I = C(dV/dT), you need a HEAVY current as the "spike" gets tiny.
>I grabbed the MTM45N05E spec. as an example.
>For a 100 nS pulse and 20 volts you need to supply .9 AMP!
>(10 nS and you need 9 AMPS! and that's for only 20 volts!)
>So, your spike driver has to have real good current ability,
>AND you must not have included the gate ballast resistor.

Your reasoning is good and I aggree with it but still FETs do not like
spikes on the gate. Perhaps there is a transmission line issue inside the
gate structure. After all, C is distributed in the device. This means that
a high voltage spike will cause high voltage at least across a small part
of the oxide before it has time to propagate. I guesstimate that at 10nsec
a 100A device will have most of the voltage applied near the gate bonding
wire for the first few ns at least. The required current for causing
breakdown should be related to the impedance of the transmission line
formed inside the device between G and S in that mode, and it would
probably be a fraction of what you calculated. There must be a solid
reason for virtually all CMOS chip manufacturers to waste space for
clamping diodes on their dies after all.

>> >My experience in LARGE FETs is the failure mode is the large dI/dT,
>> >I can tell you about blowing SEVERAL 200 amp FETs by grounding the gate!
>>
>> Afaik you can blow the FETs by grounding the gate and then applying a
>> large dU/dt on the drain.
>
>If I shut off the gate there MUST be a large change in drian voltage.
>Well, large is relative, but at least the applied voltage.
>Assuming the integral diode can clamp the inductive effects....

The substrate diode does not play here, it is reverse biased. It is
exactly the same situation as when you exceed Vds by switching an
inductive load off. If the device is fast enough it will suicide with the
inductivity of the leads alone. Again the gate resistor would help to
prevent this. The current that damages the device is supposed to appear
though Cgd across the oxide whose gate side is held firmly low (missing
gate resistor). I do not know for sure if this is what happens, but I know
that it happens.

> The coupling capacitance between D and G will
>> produce enough voltage on the gate to breakdown the oxide (the inductance
>> etc from the gate to the driver is enough for this). Is this what you mean
>> ?
>If the gate is well grounded, and the souce is well grounded,
>how do I get gate voltage?
>(If I had an inductive gate ground I can see it happening...)
>
>I have a demo with a 100 amp source of 12 volts to the drain. (MTM200N06)
>was the FET. I have a load in the drain to supply to show the current.
>1K2 watts. The Source is well grounded, the FET well Heat-sinked. I have
>an external 15 volt zener from gate to source. I apply 10 volt charge to
>the gate, all is well, 100 amps flow. (Disconecting the gate charge
>source to show the charge remains on the gate...) I apply a 1/2 inch
>piece of wire between the gate as source terminals to short the gate
>charge... The FET fails! Gate to source short! Motorola said it's the
>gate bonding wire which is inductiveenough to cause this. (They also had
>a substrate explaination....)

I have never used those FETs, but this is useful information. Thank you
for sharing it. The failure mechanism seems to be similar to with what I
describe at dU/dt above. Maybe it's the same thing that appears
differently in different devices.

Peter

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