Alan, I'm using high speed 32KByte SRAM of the type found in L2 caches.
These are 28-Pin x 0.3" devices and are available from many sources. As far
as the HP article, I would really like to take a look at that. If you can
find which issue of the HP Journal that was in, please let me know. I have
never heard of anything like this but considering it's source, I'd like to
check it out. Thanks,

    - Tom

At 10:06 25-06-02, Alan B. Pearce wrote:
I wrote:
> >    I want to keep the trigger path as short as possible. When you consider
> >the delays from the pod buffer to the trigger comparator, to the control
> >logic to the SRAM, the maximum sample rate drops dramatically...
>
>The way to expand your triggering is to use high speed static RAM chips. I
>have at home somewhere an article in an HP Journal that they did for a logic
>analyser where they did this. The RAM chips were loaded with a pattern that
>allowed the address lines to be used as the trigger bit inputs, and the data
>outputs as the trigger detection outputs. If you use byte wide devices then
>8 conditions can be set, and the trigger width is expanded in address line
>count increments.
>
>This minimises the trigger input to detect output delay to just the access
>time of the RAM plus any OR logic at the output, which should be no more
>than 2 gates deep using modern GAL chips, or it could be another 1 bit wide
>RAM. The RAM chips are then loaded from your control microprocessor, a PIC
>of course. :)) This allows setting all sorts of conditions, including "don't
>care" states into your trigger requirements.

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