>>    If we could trigger using 2 words in a sequence it would make the
>>instrument even more valuable. That would help a lot to debug programs and
>>get a nice trigger signal for the scope. Not essencial but nice. I would
not
>>mind having the memory as a circular buffer and have the trigger point
>>always in the middle of the captured memory or have it at a fixed
position.
>>The post trigger size could be fixed to make the design easier. If we have
>>enough memory the clock options can be simpler also.

>    Alexandre, these types of add-ons are part of what doomed my earlier
>project a few years ago. It collapsed under its own weight ;-)

>    I want to keep the trigger path as short as possible. When you consider
>the delays from the pod buffer to the trigger comparator, to the control
>logic to the SRAM, the maximum sample rate drops dramatically...

The way to expand your triggering is to use high speed static RAM chips. I
have at home somewhere an article in an HP Journal that they did for a logic
analyser where they did this. The RAM chips were loaded with a pattern that
allowed the address lines to be used as the trigger bit inputs, and the data
outputs as the trigger detection outputs. If you use byte wide devices then
8 conditions can be set, and the trigger width is expanded in address line
count increments.

This minimises the trigger input to detect output delay to just the access
time of the RAM plus any OR logic at the output, which should be no more
than 2 gates deep using modern GAL chips, or it could be another 1 bit wide
RAM. The RAM chips are then loaded from your control microprocessor, a PIC
of course. :)) This allows setting all sorts of conditions, including "don't
care" states into your trigger requirements.

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