.
John Dammeyer wrote:
> Any comments on Verilog verses VHDL for a first timer?   I need to
> create some customized CAN bus bit streams and a Xilinx part
> seems like  it just might be the answer.

From:
"HDL basic training: top-down chip design using Verilog and VHDL"
Douglas J Smith, VeriBest 1996 (big article)
.
.
.
  Ease of learning. If you have no knowledge of either
language, Verilog is probably easier to grasp and understand.
This statement assumes the exclusion of the Verilog compiler
directive language for simulation and of the PLI. If you include
these two, consider them additional languages you need to
learn. Also, VHDL may seem less intuitive at first for two reasons.
First, it is very strongly typed, a feature that makes it robust
and powerful for an advanced user after a longer learning
phase. Second, there are many ways to model the same
circuit, especially one with large hierarchical structures.
.
.
.

Other sources:
http://www.angelfire.com/in/verilogfaq/index.html
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html

  Mike.

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