Hi,

Any comments on Verilog verses VHDL for a first timer?   I need to
create some customized CAN bus bit streams and a Xilinx part seems like
it just might be the answer.

John Dammeyer


Wireless CAN with the CANRF module.
http://www.autoartisans.com/documents/canrf_prod_announcement.pdf
Automation Artisans Inc.
Ph. 1 250 544 4950


> -----Original Message-----
> From: pic microcontroller discussion list=20
> [mailto:PICLIST@MITVMA.MIT.EDU] On Behalf Of Tom Handley
> Sent: Friday, June 21, 2002 4:47 PM
> To: PICLIST@MITVMA.MIT.EDU
> Subject: Re: [EE]: Logic analyser trigger circuit.
>=20
>=20
>     Alexandre, I just realized I didn't answer your original=20
> question ;-)
>=20
>     I have not ported the Trigger comparator to the XCR3064XL=20
> yet but it
> will be trivial. The last revision I had posted is a 28-Bit=20
> version using a
> Lattice ispLSI1016E but as I mentioned earlier, I would not use those
> versions. Using the Xilinx devices, I've improved on the port=20
> expander, SRAM
> controllers and other designs. Back to the comparator, I want=20
> to try and get
> a full 32 Bits with the Xilinx part. Give me a day or few and=20
> I'll get back
> to you. As usual, I have not had much spare time but I'm=20
> committed to it...
>=20
>     One little `pet' project is an 8-Bit Logic Analyzer core=20
> using the above
> device. It would allow expansion in banks of 8 channels, each=20
> with their own
> clock source or combined with other banks. The core includes an 8-Bit
> Trigger comparator with Bit-enables, 15-Bit free running SRAM address
> counter, control logic (ARM, TRIG, etc), and a 15-Bit post=20
> Trigger counter.
> It is designed to support fast 32KByte SRAM. I'm having=20
> doubts about fitting
> the post trigger counter but I'm willing to make some=20
> compromises. Right now
> I'm studying various counters implemented in Verilog. A simple ripple
> counter obviously won't do due to the propagation delays. One=20
> thing for
> sure, no one will be satisfied with it as it stands. There=20
> are just too many
> trade-offs to be made and there is a good reason commercial=20
> units costs a
> fortune... However, simple data capture with fairly versatile=20
> trigger and
> clock options can go a long ways. Also, once you have the=20
> core, you have the
> foundation for a DSO by adding the analog front-end. With=20
> each bank having
> it's own clock, this provides for some interesting=20
> combinations of digital
> and analog data capture. Right now, I'm planning on a second=20
> CPLD to handle
> the `glue logic' to support up to 4 banks or 32-Bits as well=20
> as the host
> interface.
>=20
>     You mentioned using a "palmtop". One of the advantages of=20
> these devices
> are their low current consumption. From the data sheet, at=20
> 20MHz it draws
> around 4ma, around 200ua at 1MHz, and near 0ma when static.=20
> This obviously
> depends on the design. The Lattice device draws around=20
> 60-90ma... The Mach
> devices were an improvement but the equivalent parts did not=20
> have the extra
> 4 inputs which I relied upon for some designs like the=20
> Trigger comparator.
> Also, these devices are faster, comming in 6, 7, and 10ns=20
> versions. The
> $6.50 price I mentioned in my previous message was for the=20
> 6ns version. The
> 10ns version is only $3.20. You can find the Xilinx on-line store at:
>=20
      http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/EN/Catalog

    - Tom

At 10:02 20-06-02, Alexandre Guimar=E3es wrote:
>Hi,
>
>     Does anyone have Tom Handley's 24 bit trigger circuit for a PLD
archived
>that could send to me ? I was not able to find where I put it and I am
in
>the proccess of making a small DSO and logic analyser and would love to
take
>a look at tha file. His site is down and I was not able to send email
to him
>also.
>
>     I am trying to do a small thing that could be plugged to a palmtop
and
>help with field debugging. Most of the projects I see around are either
too
>fast or just deal with audio frequencies. I need something that can
sample
>at around 100 khz and can do somewhat complex triggering. I think a
fast AVR
>or Ubicom part with external SRAM should be able to achieve it with
very
>little circuit complexity.
>
>Best regards,
>Alexandre Guimaraes

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