Alexandre, I just realized I didn't answer your original question ;-) I have not ported the Trigger comparator to the XCR3064XL yet but it will be trivial. The last revision I had posted is a 28-Bit version using a Lattice ispLSI1016E but as I mentioned earlier, I would not use those versions. Using the Xilinx devices, I've improved on the port expander, SRAM controllers and other designs. Back to the comparator, I want to try and get a full 32 Bits with the Xilinx part. Give me a day or few and I'll get back to you. As usual, I have not had much spare time but I'm committed to it... One little `pet' project is an 8-Bit Logic Analyzer core using the above device. It would allow expansion in banks of 8 channels, each with their own clock source or combined with other banks. The core includes an 8-Bit Trigger comparator with Bit-enables, 15-Bit free running SRAM address counter, control logic (ARM, TRIG, etc), and a 15-Bit post Trigger counter. It is designed to support fast 32KByte SRAM. I'm having doubts about fitting the post trigger counter but I'm willing to make some compromises. Right now I'm studying various counters implemented in Verilog. A simple ripple counter obviously won't do due to the propagation delays. One thing for sure, no one will be satisfied with it as it stands. There are just too many trade-offs to be made and there is a good reason commercial units costs a fortune... However, simple data capture with fairly versatile trigger and clock options can go a long ways. Also, once you have the core, you have the foundation for a DSO by adding the analog front-end. With each bank having it's own clock, this provides for some interesting combinations of digital and analog data capture. Right now, I'm planning on a second CPLD to handle the `glue logic' to support up to 4 banks or 32-Bits as well as the host interface. You mentioned using a "palmtop". One of the advantages of these devices are their low current consumption. From the data sheet, at 20MHz it draws around 4ma, around 200ua at 1MHz, and near 0ma when static. This obviously depends on the design. The Lattice device draws around 60-90ma... The Mach devices were an improvement but the equivalent parts did not have the extra 4 inputs which I relied upon for some designs like the Trigger comparator. Also, these devices are faster, comming in 6, 7, and 10ns versions. The $6.50 price I mentioned in my previous message was for the 6ns version. The 10ns version is only $3.20. You can find the Xilinx on-line store at: http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/EN/Catalog - Tom At 10:02 20-06-02, Alexandre Guimar=E3es wrote: >Hi, > > Does anyone have Tom Handley's 24 bit trigger circuit for a PLD= archived >that could send to me ? I was not able to find where I put it and I am in >the proccess of making a small DSO and logic analyser and would love to= take >a look at tha file. His site is down and I was not able to send email to= him >also. > > I am trying to do a small thing that could be plugged to a palmtop and >help with field debugging. Most of the projects I see around are either too >fast or just deal with audio frequencies. I need something that can sample >at around 100 khz and can do somewhat complex triggering. I think a fast= AVR >or Ubicom part with external SRAM should be able to achieve it with very >little circuit complexity. > >Best regards, >Alexandre Guimaraes -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads