Alexandre, as Dwayne mentioned, my site has moved to:

       http://tomhandley.home.mindspring.com/wilbure.htm

    However, I would not bother with the old Lattice versions posted there.
I've been spending the last few months converting my Lattice and Mach
designs over to Xilinx... The Lattice parts are nearly obsolete, expensive,
and draw a `terrible' amount of current... It's frustrating as I've been
with Lattice for years and have their commercial Design Expert package, but
it's time to move on. At the low end, I'm using the Xilinx CoolRunner XPLA3
family, in particular, the XCR3064XL 64 macrocell device which comes in a
PLCC-44 package amongst others. This is similar to the Lattice ispLSI1016E
yet it draws a fraction of the current and is priced about 75% less. It has
a 3.3V core with 5V tolerant I/O. I use a low-dropout, 3.3V linear regulator
in a TO-92 or surface mount package. These regulators are widely available
and low cost. Also, putting a regulator right at the device has other
obvious benefits. You can order these devices directly from Xilinx in single
and small quantities. The last order I placed was last month and they were
still around $6.50/ea + $10 shipping in the USA.

    Lattice's Design Expert package and Xilinx's WebPACK are similar since
the same companies provide the tools (Verilog, VHDL, ModelSim, etc) so
moving from one to the other is fairly easy but you will still have some
homework to do as each vendor adds their own `twist' on things and then
there is the differences in architecture which require a different set of
constraints, fitter reports, timing analysis, simulation, etc. If you have
used Lattice's schematic capture package you will find some similarities but
it's really a different package and takes some getting use to, if for no
other reason, to `un-learn old habits' from the former. One thing that
immediately struck me is that you can not lock pins at the schematic level
but the Chip Viewer makes it easy to assign pins and you can always edit the
pin constraints file which is what I prefer after letting the fitter make an
initial pass. The overall flow of the Project Navigator is very similar.

    For JTAG programming, the Xilinx cable is a simple buffered parallel
port interface and a reference schematic is available on their site. Unless
you plan on using 1.8V core devices (ie: CoolRunner II), the cable will work
fine with 3.3V and 5V devices. If you looked at the Lattice ISP Download
cable schematic, this is similar. They use two 74HC125s and some passives.
Regarding dual-use of the JTAG pins, in the Lattice device, you have the
option of reserving the JTAG pins at the sacrifice of 4 dedicated inputs.
This is set as part of the properties during the fitting process. In the
CooolRunner devices, there's an external Port-Enable pin which I prefer.

    Finally, if you or anyone else are interested in the Xilinx family and
designing their own CPLDs, first go to their site and download WebPACK and
all the manuals, app notes, JTAG cable schematic, etc.

       http://www.xilinx.com/

    Then, go directly to:

       http://www.al-williams.com/pictutor/

    I can not believe I have not run across Al's site before! On there, Al
has provided an `Absolutely Outstanding' tutorial on using WebPACK with
Xilinx's XC95 devices. He also has a nice protoboard to get you up to speed
quickly. His tutorial applies directly to many of the Xilinx devices and he
even touches on Verilog and ModelSim with examples, two very complex
subjects in their own right. I wish I had know about this several months ago
as I had to do it the `old fashioned way'... RTFManuals ;-)

    You will still have a lot of studying to do, especially if you are new=
 to
this but Al's site can really help you get up to speed with simple,
practical examples. He obviously has a great deal of experience with Xilinx,
Altera, and CPLDs in general.

    Great work, Al!

    - Tom

At 10:02 20-06-02, Alexandre Guimar=E3es wrote:
>Hi,
>
>     Does anyone have Tom Handley's 24 bit trigger circuit for a PLD=
 archived
>that could send to me ? I was not able to find where I put it and I am in
>the proccess of making a small DSO and logic analyser and would love to=
 take
>a look at tha file. His site is down and I was not able to send email to=
 him
>also.
>
>     I am trying to do a small thing that could be plugged to a palmtop and
>help with field debugging. Most of the projects I see around are either too
>fast or just deal with audio frequencies. I need something that can sample
>at around 100 khz and can do somewhat complex triggering. I think a fast=
 AVR
>or Ubicom part with external SRAM should be able to achieve it with very
>little circuit complexity.
>
>Best regards,
>Alexandre Guimaraes

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