Until of course you go to flip chip techniques, no? Or do flip chips still
have all the I/Os on the egde of the die? TTYL

> CPLDs are not a cheap way to add lots of pins.
> the reason is silicon area - lots of pins = more space needed around
> the edge of die = bigger die = fewer chips made per wafer = more
> expensive chips.
> This is the reason you never see chips with lots of pins but not so
> many gates - as the chip has to be big to accommodate the pins, the
> internal die area adds no cost, so they fill it up with gates or
> whatever.

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