This damn project seems to be more trouble than it's worth, if anyone =
mathematically minded can help me with this I would be very grateful.

Okay, I have a ADC input that has full range (ie. 0 to 255) and basically =
it needs to cause a delay like this:

ADC_VAL                Delay in cycles

0                              400
255                          3200

So this really means that each decimal '1' of ADC_VAL equates to 11 cycles =
extra delay, ok so its not exactly 11 but it'll do, it'll only be 5 cycles =
off at the end.=20

Now here comes the part that is giving me grief, I can do 3205 cycles with =
a two tier nested delay, but there are two values that affect the delay =
time, the inner and outer loop variables.
I think the way to do it would be too divide the required delay into 255 =
to get a carry (whole numbers) and the rest would go into the inner loop =
ie. the stuff after the decimal point to 3 sig figs.

This would be all well and good except for the fact that Nikolai Golovchenk=
o's division code uses a whopping great 400 cycles.
I can't think of anything I can do, as I require two values I can't even =
do a computed jump into a 255 long retlw table.

Is anyone able to give me a poke towards a solution?

Jonathan Starr

R&D Technician
Electronix Limited

Tel +44 (0)1993 700510
Fax +44 (0)1993 700511


e-mail jonathans@electronix.co.uk

web www.electronix.co.uk

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