Just thinking about it.

What about a simple integrator/comparator?  It would take very few
components, and with a well defined signal could be just as reliable as
a digital system.

The pulse length is known, so charge up a capacitor each time the pules
comes along.  Trigger a comparator when the cap is three pulses full,
and the comparator also drains the cap with a transistor.

You could expand on this with a schmidt trigger or window comparator -
by designing a resistor in series with the transister you can define the
output pulse length.

Noise is just as much an issue here as with other circuits, but the
filter is built in, and if you have enough noise to make up for the
power of an additional pulse then you've got more serious problems than
dividing by three...

I imagine 4 passive components, 1 transister and an 8 pin chip.  It
could take up less space than the decade counter alone.

-Adam

Russell McMahon wrote:

>>>I love these "cheap" challenges!
>>>
>>>
>
>OK here's another then ...
>This is for another application (and another customer) from the last one.
>
>As noted in the last challenge thread, standard flip flops and counters
>without Schmitt trigger inputs have limits on maximum rise and fall times.
>Real world signals can challenge these severely.
>
>I have been asked to divide a digital signal by 3.
>The input is a 3 volt signal produced by either a hall sensor or a reed
>switch.
>The signal idles at 3 volts and drops to ground for a brief period as the
>sensor is triggered.
>Input speed is from about 3 to 70 cycles per second (on a motor pulley).
>
>Finished cost is paramount.
>
>Using HC CMOS ICs I tried using a standard dual JK divide by 3 (2 gates in a
>single package with no glue)(7473, 7476, ?4027 etc). While the JK flip-flops
>involved were happy with lab generated signals they resolutely refused to
>behave with real world generated signals (from hall sensor and/or reed
>switch). The results were intermittent. Divide by 3 3 3 2 3 3 2 4 2 3 3 3 6
>3 .....
>
>I have now gone to a 4040 counter with a naughty two diode and resistor "AND
>gate" to drive the reset. Resistor from RESET to Vcc. Diodes from Q1 and Q3
>to RESET (Anode ends). When both outputs are high the diodes block, resistor
>pulls up reset line and both Q's fall again. The resultant reset pulse is
>therefore "just long enough:" to cause reset and has the potential to only
>partially reset the IC. As I am using just the first two stages the chances
>for erroneous operation MAY be reduced compared to higher divide ratios.
>
>The 4040 has a Schmitt trigger clock input which cures the input rise time
>problem but this circuit substitutes a potentially fatal race condition for
>the JK's input rise time limitation. I can however "design" for the 4040's
>behaviour across a spread of device parameters. In testing it seems
>remarkably immune to improper performance and the application can in fact
>stand the occasional mis-reset (even one in ten would be OK!) but I'm still
>somewhat nervous about such "improper" methods. Adding a capacitor to the
>reset line potentially improves operation but doe not seem necessary. Adding
>a 2 stage RC filter would allow some proper reset hold time but seems even
>less necessary.
>
>Anyone want to implement a more elegant asymmetric divide by 3 on an
>asymmetric 3 to 70 Hz input signal at a lower all up cost than a CD4040, 2 x
>1N4148's and a 100k resistor :-) ? Best cost from another source (method
>unknown) was $US1 manufacturing cost per unit in moderate volume.
>
>
>
>        Russell McMahon
>
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>
>
>
>
>
>

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