On Tue, 28 May 2002, Morgan Olsson wrote:

> Vasile Surducan wrote:
>
> >10k and 2pF ( typically for 1N4148 ) means a glitch of about
> >10 exp+3 x 2 exp -12 =3D 20nS .
>
>
> 1) I=B4d say a *typically* 20ns glitch worries me.  We must use max, not =
typical value here.
>
> 2) For the second case i wrote about, (diode recovery), the glitch will b=
e the recovery time PLUS this *typical* 20ns.
>
>
> >You haven't that fast cmos gate to feel this glitch ( 4000 series at
> >3V...15V ) so don't worry.
>
> Motorola datasheet 4017, Clock pulse width: typical 125ns@5v, 35ns@15V
>
> Example:  if that 20ns calculated typical glictch is actually 30ns on 10%=
 of your produced units, and in 10% of theese units there is cirquits that =
react to lower than that clock pulse, then 1% of produced units fail...
>

  Yes, but you don't take in your computation the input gate capacity...
  which is more important than parasitic diode capacity.
  I'm sure you will have 0 fails. Try it. But not at 90C.

best regards, Vasile

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