To be able to predict this would be ideal, as I'm getting a lot more ISR calls that I care for, but I felt uneasy about my calculations in trying to correct for this. Here's the top part of my ISR code: ORG 0x04 goto ISR ISR: ;----- Save W and STATUS registers ----- movwf TMP_W ; Save W swapf STATUS,W ; Get status (w/o affecting status bits) movwf TMP_ST ; Save status bcf STATUS,RP0 ; Reset to bank 0 ... bcf STATUS,RP1 ; ... movlw SCALER0_ADJ addwf TMR0,F ; Adjust TMR0 f/ints every 193 counts ;----- [ Freq. here = 1.544Mhz / (4 * 193) ] ----- ;----- Divide by 200 to get 1/10-sec pulses ----- decf SCALER1,F If I start from the clock cycle that generated the TMR0 interrupt, then (I assume) that the prescaler just hit 0, the TMR0 counter just transitioned from FF to 0, and the PC is now set to 0x04, ready to execute that instruction -- not executed yet. PS = 1, and it's ready to execute the first ISR instruction. PS = 2, when ready to execute swapf ... ...etc, etc, etc, until... PS = 7, when ready to addwf TMR0,F (SCALER0_ADJ is 193). PS = 8 (which is PS = 0 on a 1:8 prescaler), should occur when the TMR0 valve has been adjusted, and this will get reset to 0, so no change. The timing worked out just right in this case, but TMR0 has one extra count. Seems like just a matter of loading TMR0 with 192 instead of 193? There are a lot of assumptions on my part here, so I'm a bit uneasy with this. Cheers, -Neil. -----Original Message----- From: pic microcontroller discussion list [mailto:PICLIST@MITVMA.MIT.EDU]On Behalf Of Jinx Sent: Saturday, May 18, 2002 12:34 AM To: PICLIST@MITVMA.MIT.EDU Subject: Re: [PIC]: External clock... > > Does it even matter? A quick calculation tells me with > > a 1:8 prescaler, say for example the prescaler gets reset > > to 0 whenever it just hits its 7th pulse from start. > > That means that it loses 7*4*osc-period units of time. > > It would do this whenever TMR0 gets reset to 193, which > > means every 8*4*193*osc-period units of time. So time > > loss ~= 1 pulse in every 222. That means about 39.5 days > > a year. You can compensate for resetting the PS. After the timer generates an interrupt there are a predictable number of cycles before you reload it. By adding up the cycles needed to GOTO IRQ, BCF T0IF, MOVLW .193, MOVWF TMR0 etc etc and any other inherent or coded cycles occur you can calculate how often you need to make an adjustment so that in the long term you minimise the error -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! email listserv@mitvma.mit.edu with SET PICList DIGEST in the body -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! email listserv@mitvma.mit.edu with SET PICList DIGEST in the body