----- Original Message ----- From: "Pic Dude" To: Sent: Friday, May 17, 2002 10:45 PM Subject: Re: Antwort: [PIC]: External clock... > Bob, > > The calculation (adding 2) is straightforward, but what > do you mean by "jitter". I remember seeing something on > this a while back (either in the archives or on piclist.org), > but never got a clear explanation of jitter. Care to > add some enlightenment? I am not sure if it happens with TMR0 or not, but some interrupt sources have different latencies depending on whether a one- or two-clock instruction is executing when the interrupt occurs. > The datasheet also states that the prescaler is cleared > whenever TMR0 is written to. My understanding is that > the pre-scaler "counts" before TMR0 (since it's the TMR0 > transition that triggers the interrupt), so I'm wondering > if modifying TMR0 will cause the clock to run slow due > to the prescaler getting reset when it shouldn't? Yeah, I assumed you were not using the prescaler. This technique will _not_ work with the prescaler at any setting other than 1:1. > Does it even matter? A quick calculation tells me with > a 1:8 prescaler, say for example the prescaler gets reset > to 0 whenever it just hits its 7th pulse from start. > That means that it loses 7*4*osc-period units of time. > It would do this whenever TMR0 gets reset to 193, which > means every 8*4*193*osc-period units of time. So time > loss ~= 1 pulse in every 222. That means about 39.5 days > a year. > > That's pretty significant, if it really happens. Does it? > Or am I totally off on the wrong tangent here? No, you aren't off on a tangent. This is exactly the thing that can happen. > Thanks, > -Neil. -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads