Erm.. and now I've woken up.... ----- Original Message ----- From: "Jon Baker" To: Sent: Wednesday, May 01, 2002 9:02 AM Subject: Re: [PIC]: CAS/RAS > for cAS before RAS: > CAS low for counter=1 to n_rows RAS low wait RAS high next CAS high > > Does CAS go LOW, then RAS gets cycled for each ROM address, then CAS > > goes HIGH again? > > I think that is a hidden refresh, and not all dram supports it. Hidden refresh is a type of cas before ras refresh but differs in that it can take place immediately after a data transfer and before cas is returned high again. You can also pulse ras more than once before returning cas high to do a burst refresh- hidden refresh has the addvantage that the data presented on the bus after a read remains valid even though you are refreshing the dram. -- Jon Baker I'll be quiet now. -- http://www.piclist.com hint: To leave the PICList mailto:piclist-unsubscribe-request@mitvma.mit.edu