Thanks to all who replied; Ted, Olin and Chris,
you all gave me good ideas...


On Wed, 20 Mar 2002, Chris Loiacono wrote:

> > I have to synchronize a zero cross main signals with an
> > output nibble on
> > both rising and falling edge.
>
> Meaning that you need to output 2x per cycle or once?

Some time only once ( when the output nibble state remains unchanged a
numbers of mains periods ) other time twice ( the output is unchanged
only one half period of the mains)

>
> > I have done this in hardware using one 4093 and a few resistors,
> > capacitors and one zenner for detection and a 74ls373 for command.
>
> First, I can assume (I hate that word!) that there is no isolation from the
> mains because none is mentioned - so what protects the zener, the 4093 &

There is no isolation, and will not be any isolation for 628 either,
except a resistor lo limit the mains ( input divisor is 230 K + 10K to ground,
in parallel with 10K is a 5v1 zenner )
With nibble i'm firing some triacs ( no problem here )

>
> > I'm not sure if the best choice on a PIC will be to use rb0 as zero
> > cross detection interrupt.
>
> I would think you would have to use the highest priority int source in order
> to synchronize closely, but then, If I am not mistaken, you can only have
> this respond to either a high or low, depending upon the option register
> state. It seems you'll have only one input state for both ZC's with the
> hardware you described, so this should work if you don't need to
> differentiate the data sent at each 1/2 cycle of the mains.

With the structure I've mention both alternance zero crossing are sensed.
( with a small derivating circuit R+C and then another trigger, 3 gates
from 4093 are used )

>
> >The nibble must be outputed
> > synchronously with the rising edge of the mains signal and shutted off
> > after a desired time period on the falling edge of the same signal.
>
> Do you  mean that you only want to send the nibble during a portion of the
> positive 1/2 cycle?
> (OK, this is a redundant question. Sorry, but I understand pictures better
> than text.)
> If so, I have found that hardware that differentiates the positive 1/2 cycle
> from the negative used with a high-priority interrupt is much easier to work
> with. It's still simple hardware, and simpler code. I guess that's why my ZC
> hardware is typically different from what you described here....
>
> > I think also interrupt on change could satisfy this request
> > but I want to
> > know other opinions.
>
> Well, there's mine - which may or may not be valid....
> Chris


  Thanks, Vasile

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