> If this is expected to _truly_ synchronize two PICs one might expect that
> they will run clock-for-clock identically if MCLR is brought up with an
> appropriate setup time relative to OSCin (assuming an external osc).
>
> This would imply that the internal clock phasing would be set relative to
> the rising edge of MCLR.
>
> This would also imply very small jitter even if MCLR is not synchronized
to
> OSCin (or for an internal osc) -- not more than 1 cycle of the clock!

I agree with your reasoning, but I'm not willing to read that much into
their statement without verifying it.  I can see how they might consider two
PICs "synchronized" if they are within a instruction or two of each other.

I think the answer depends on whether the Q clock is still running during
reset.  If not, then it would probably start at Q0 on the next oscillator
edge after MCLR high like you said.

I just looked over the timer sections in a data sheet, and it appears they
don't run from the instruction clock during MCLR.  The data sheet is vague
about what happens to timer 0 and 1 during MCLR, but timer 2 definitely does
not run.  This supports the idea that the Q clock is not running, which
makes your interpretation more likely.  I'd still want to test it or get a
definitive statement from Microchip before relying on this though.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, olin@embedinc.com, http://www.embedinc.com

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