>Does anyone know if there are standard package
>dimensions for packages like:
>sop or ssop, and where I might find them?

The answer is "Yes and No"

I have just been through the loop of designing my first SMD board, and every
chip seems to have a slightly different outline (sigh).

Perhaps it is just that the guy overseeing the CAD system is pedantic, but
when a chip from manufacturer A is specified as being an SO-8 package, do
not automatically expect it to be the same as chip from manufacturer B
spec'ed as an SO-8. In many cases it may well solder to the same pad set,
but could end up with lead ends off the pads because it is 0.5mm wider, or
some similar subtle difference.

The detail is in the actual package dimensions. We have standardised on the
JEDEC package numbering in our CAD system. This is usually stated by the
chip manufacturer in the package outline drawing on the chip data sheet.
Except that some manufacturers like TI do not put the package outline on the
data sheet, but have a separate datasheet for all outlines :)

At the end of the day, check the package outlines carefully! The chip you
are buying may actually be in a TSSOP package, not an SO- series package.

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