> > My idea too, but I can not find any data on how immediate.
>
> They only say "immediately".  I don't know if the internal Q clock is
runing
> during MCLR, so it might have to wait for the next Q0 phase, maybe two to
> get the pipline going.  For the 16F87x (DS3029C) the pertinent paragraph
is
> in section 12.8 on page 124: "If MCLR is kept low long enough, the
time-outs
> will expire.  Bringing MCLR high will begin execution immediately.  This
is
> useful for testing purposes or to synchronize more than one PIC 16F87x
> device operating in parallel."

Hm....

If this is expected to _truly_ synchronize two PICs one might expect that
they will run clock-for-clock identically if MCLR is brought up with an
appropriate setup time relative to OSCin (assuming an external osc).

This would imply that the internal clock phasing would be set relative to
the rising edge of MCLR.

This would also imply very small jitter even if MCLR is not synchronized to
OSCin (or for an internal osc) -- not more than 1 cycle of the clock!

Bob Ammerman
RAm Systems

--
http://www.piclist.com#nomail Going offline? Don't AutoReply us!
email listserv@mitvma.mit.edu with SET PICList DIGEST in the body