> Also, the PIC16F874 datasheet is confusing when it talks about how
> to read the error flag bits in the receiver.

Don't blame this on the manual.  Actually it's quite clear.

> It says that the FERR
> flag gets buffered in the FIFO, but the block diagram wouldn't suggest
> that.

The block diagram is just that, not a schematic.

> Then it says to read the error flags before requesting a byte
> from the FIFO. If FERR flags are buffered in the FIFO wouldn't this
> mean that you'd be reading the wrong data unless you check the FERR
> bit after you get data from the FIFO? Can someone please explain this?

In section 10.2.2 "USART Asynchronous Receiver" on page 101 of DS3029C near
the bottom of the second colum of text it says "Reading RCREG will load bit
RX9D and FERR with new values, therefore, it is essential for the user to
read the RCSTA register *before* reading the RCREG register in order not to
lose the old FERR and RX9D information".  I don't think I can explain it any
better than that.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, olin@embedinc.com, http://www.embedinc.com

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