> I thought that the 18C series does away with paging.  Am I wrong?
>
> Jeff

The 18C series does indeed do away with code paging.

It still has data banking, however. The banking issues are greatly
alleviated by a several clever addressing schemes:

Direct addresses are encoded in instructions as a single-bit "A" field and
and 8-bit offset.

If A is set to one, then the instruction references the 'access bank'. This
bank is actually the first 128 bytes of data memory (in addresses 0..127 of
the access bank) and the last 128 bytes of data address space (mapped to
addresses 128..255 of the access bank). Since all the special function
registers (SFR's) are conveniently in that last 128 bytes of the data
address space they can be referenced by just using a appropriate address in
the access bank.

If A is set to zero, then the 8-bit offset is relative to the currently
selected 256-byte bank. Different chips in the 18C series have different
numbers of banks implemented. The architecture supports a maximum of 16
banks or 4K bytes (minus the SFRs at the highest addresses).

By presetting the bank select register to a fixed value, and then leaving it
alone, your code can directly reference 384 bytes of data memory (128 in
access bank and 256 in selected bank) and all SFRs without having to perform
any banking operations.

Indirect addressing is via any one of three (yep, 3!) FSRs, each of which
can contain a full 12-bit data memory address. You can load an FSR with a
12-bit address, in a single two-word instruction, and without disturbing W
by using the "LFSR n,addr" instruction (which was broken on some early
silicon). You access the memory location pointed to by FSRn by simply
referring to INDFn, for n={0,1,2}. You can also adjust thge FSR at the same
time you process the value it points to be referring to "POSTINCn" (FSR is
incremented after the operation), "POSTDECn" (FSR is decremented after the
operation) or "PREINCn" (FSR is incremented before the operation).

Finally, you can index into a structure or array to be an FSR by placing the
desired offset in W and then referring to "PLUSWn".

All-in-all a pretty flexible arrangement.

Here is a little sample that copies 100 bytes from a buffer called "A" to a
buffer called "B". Note that this code doesn't have to worry about banking
issues at all.

    movlw    100
    movwf    count,A        ; variable in access bank
    lfsr    0,A                    ; point to buffer in any bank
    lfsr    1,B                    ; and another one
loop:
    movff    POSTINC0,POSTINC1
    decfsz    count,F,A
    bra        loop

I am not positive the MOVFF instruction is legal with the POSTINC arguments.
There are several SFRs where MOVFF is documented _not_ to work and I don't
remember if the POSTINCn's are some of them. If this is a problem then the
MOVFF could be replaced with:

    movf    POSTINC0,W
    movwf    POSTINC1

which would take the same memory and time and give the same result, except
that STATUS and W would be affected.

Bob Ammerman
RAm Systems

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