> Nope, that doesn't seem to be it.  I added the
> following code to the end of all places where the
> EEPROM is written to, and it always ends up in a WDT
> time-out.

EEPROM writes can be quite slow.  Is it possible that the watchdog triggers
before the write is complete?  If so, you could kick the dog in the wait
loop.

>         btfss   PIR1, EEIF
>         goto    $-1
>         bcf     PIR1, EEIF
>
> I think this may not have been working because it is
> an interrupt flag, and I have all interrupts disabled,
> therefor the flag may be inactive.

Interrupt flags get set whether interrupts are disabled or not, so this
method is perfectly fine when interrupts are off.

> And if clearing
> the EEIF flag was such an important part in properly
> writing to the EEPROM I would like to think that more
> mention to it would have been made than in that small
> section of 13.2.

I think they documented this very well.  You don't really want the same
information in too many places because it would make the manual too tedius
to read.  The last two sentences of section 13.4, "Writing to the EEPROM
data memory", near the top of the second column on page 93 of DS40300B read
"The user can either enable this interrupt or poll this bit.  The EEIF bit
in the PIR1 register must be cleared by software".  I can't think of a
better place to put this, nor do I find it ambiguous.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, olin@embedinc.com, http://www.embedinc.com

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