Douglas Butler <dbutler@IMETRIX.COM> wrote:

|The obvious solution to both latency and uncertainty is an external AND
|gate.  When you want the signal propagated you just turn on the AND
|gate, and turn it off when you want to stop.  Latency is the delay of
|the gate and uncertainty is nil.

I'm not trying to design a circuit.  I'm trying to determine the best that
the firmware in an existing design could be doing.  There is no external gate.

|If you must do it in software look at what clock phases the bit test and
|set operations work on.

Could you expand on this?  It isn't clear to me how that timing would affect
the uncertainty.

|Sherpa Doug
|
|> -----Original Message-----
|> From: Dan Lanciani [mailto:ddl@DANLAN.COM]
|> Sent: Friday, February 08, 2002 4:11 AM
|> To: PICLIST@MITVMA.MIT.EDU
|> Subject: [PIC]: minimum uncertainty input->output
|>
|>
|> Given a 16C54 class device, what is the minimum
|> uncertainty/jitter with
|> which a change in a general input can be propagated to a
|> general output?
|> My first thought is that a bit test & skip/goto loop gives a
|> three instruction
|> cycle uncertainty, but I'm probably missing a trick.  I don't
|> care (within
|> reason) about minimizing the latency, just the absolute
|> uncertainty in the
|> latency.

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