Jon Baker <jon@HAYSEED.NET> writes:
> I would very much appreciate you enlightening me. Are you thinking
> some complicated external hardware shift registers or something 'cause
> I'm stuffed if I can see how to get that high a bitrate even if it is
> for 50us without having to use one of the SX chips.

A little bit of external hardware, but nothing really complicated.
External oscillator, 74HC166 shift register, 74HC74 flip flop, and a few
gates.  You start with twice the bit rate for the PIC clock.  You divide
by two for the shift register clock.  The PIC needs four clock cycles
per non-branching instruction, so you get four instructions (16 oscillator
clocks) per data byte.

You do the opposite of what my closed-caption decoder does.  The CC
decoder samples line 21 at five times the bit rate, dumping the raw
samples into memory.  Then it uses the time during other scan lines to
decode it.  For encoding, it easier, because you don't need
oversampling.  You spend the non-blanking time of n scan lines
(hopefully for a small value of n) formatting the buffer while
generating black video output.  Then you generate one scan line of
"video" from the buffer.


                                          PIC
                                         +-------------------------+
                                         |                         |
          +------------------------------|>                        |
          |                              |                         |
          |   +------------+-------------|A0                       |
          |   |            | ___         |                         |
          |   |            +-|  \        |                         |
          |   |   --------   |   )O--+   |                         |
          |   +---|D    Q|---|__/    |   | B0 B1 B2 B3 B4 B5 B6 B7 |
          |       |      |    '00    |   +-------------------------+
          +--|>O--|>   Q*|           |      |  |  |  |  |  |  |  |
          |  '04  --------           |      |  |  |  |  |  |  |  |
          |        74HC74            |      |  |  |  |  |  |  |  |
          |                          |   +-------------------------+
          |   +--------------+       |   | D0 D1 D2 D3 D4 D5 D6 D7 |
          |   |              |       |   |                         |
          |   |   --------   |       +--O|PE                       |
          |   +---|D    Q|   |           |                         |
+------+  |       |      |   |           |                         |
| 13.8 |--+-------|>   Q*|---+-----------|>                     Q7 |----> to
| MHz  |          --------               |                         |    video
+------+           74HC74                +-------------------------+
                                          74HC166

Add'l circuitry to generate blanking and sync from PIC outputs not shown.
The '04 inverter can obviously be replaced with another NAND gate from the
'00.  Or all the 74HC stuff can be put into one CPLD.

One flip-flop is used to divide the oscillator clock to get the shift
clock.  The other is used together with the gates to produce a parallel
load enable for the shift register.  The parallel enable needs to be
only one dot clock wide, but the narrowest pulse the firmware can
produce on a port pin is two dot clocks wide.  The firmware generates a
two dot clock wide positive-going pulse, we use a flip-flop to delay it
one dot clock, then NAND it with the undelayed pulse producing a
negative pulse one dot clock wide.  The inverter on the flip-flop clock
is to make it negative-edge-triggered, so that the parallel load enable
of the shift register will be stable during its clock input transition
(rising edge).

The code to generate the active video is an unrolled look like this:

        movf    buf+0,w
        movwf   portb
        bsf     porta,0 ; pulse load input to shift register
        bcf     porta,0

        movf    buf+1,w
        movwf   portb
        bsf     porta,0 ; pulse load input to shift register
        bcf     porta,0

        ; repeat 42 more times using successive bytes of the buffer

        movf    buf+44,w
        movwf   portb
        bsf     porta,0 ; pulse load input to shift register
        bcf     porta,0

        movlw   0       ; generate black the rest of the time
        movwf   portb
        bsf     porta,0 ; pulse load input to shift register
        bcf     porta,0

Note that the bcf and bsf instructions used to manipulate PA0 for
the shift register load could modify any other port A outputs if
the level on the pins was not the level in the output latches (if
there is non-trivial loading on those pins).  Not a problem if
they are used as inputs.

Email me if you need my address to send the check for consulting fees
and/or royalties.  Just kidding.  Obviously I wrote this up for the fun
of it.  Anyhow, I haven't tested it, so I don't guarantee that it works.

With an SX, you could do it entirely in software.

Good luck!
Eric

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