Tony wrote: > This works when simulated with MPLAB. > > Some addresses like 0x1B forced MPLAB to complain so I used the > Mnemonics for them. > > STEE bsf PORTB,LED > bsf STATUS,RP0 ; <<<< changed from bcf > bcf STATUS,RP1 > movlw 0x00 > movwf EEADR ; <<< MPLAB complained about 0x1B > movlw 0x53 > movwf EEDATA ; << MPLAB complained > bcf STATUS,RP0 ; <<<<<<<< added > bcf PIR1,EEIF > bsf STATUS,RP0 > > WRITE bcf INTCON,GIE > bsf EECON1,0x2 ; eecon1,wren > movlw 0x55 > movwf EECON2 ; eecon2 > movlw 0xAA > movwf EECON2 ; eecon2 > bsf EECON1,0x1 ; eecon1,wr > bcf STATUS,RP0 ; <<<<< added = RAM Pg 0 now > > WREND btfss PIR1,EEIF > goto WREND > > bcf PIR1,EEIF > bsf STATUS,RP0 ; <<<<<< added = RAM Pg 1 now > bcf EECON1,0x2 ; eecon1,wren > bcf STATUS,RP0 > ; <<<<< deleted - bcf status,rp1 > bcf PORTB,LED > > ENDWR goto ENDWR Is there any reason why you can't do what I have done below ? This is based on a write routine I wrote last week. I haven't had any problems with it, but maybe I've been lucky ?? Instead of polling PIR1,EEIF you poll EECON1,WR which is cleared (according to data sheet DS40300B) at the completion of the write cycle. This saves a couple of bank switches and clearing of EEIF bit instructions. STEE bsf PORTB,LED bsf STATUS,RP0 ; bcf STATUS,RP1 ;bank 1 movlw 0x00 movwf EEADR movlw 0x53 movwf EEDATA ;load address and data WRITE bcf INTCON,GIE bsf EECON1,0x2 ; eecon1,wren movlw 0x55 movwf EECON2 ; eecon2 movlw 0xAA movwf EECON2 ; eecon2 bsf EECON1,0x1 ; eecon1,wr WREND btfsc EECON1,0x1 ;wait for WR bit clear goto WREND bcf EECON1,0x2 ; eecon1,wren bcf STATUS,RP0 ; bank 0 bcf PORTB,LED ENDWR goto ENDWR James -- http://www.piclist.com hint: To leave the PICList mailto:piclist-unsubscribe-request@mitvma.mit.edu