--- "Alan B. Pearce" <A.B.Pearce@RL.AC.UK> wrote:

Although this will increase the cost and many may not like it, but
here's the idea:
Please tell me if in your opinion these will work.

> If you have a transistor without a base protection resistor, to drive
> a high
> current load, the read part of the instruction will detect a 0, and
> rewrite
> it as a 0 if the instruction did not modify that bit. This applies to
> any
> load on the port that may hold the output down at a 0 level during
> the read
> part of the cycle.

 Add a buffer between the PIC port and the load  : an inverting or non
inverting buffer/gate. AFAIK there are some high current capable
buffers in CMOS technology for such interfacing and they will take the
burden of supplying adequate drive for the transistor.

> The second part of the problem occurs when driving a load that has
> enough
> capacitance associated with it to form a significantly long time
> constant at
> the fastest speed you access the port. This could be due to the input
> capacitance of a power FET, or wiring to some remote part of the
> hardware.
> This is usually only a problem if you use consecutive instructions to
> do BSF
> on separate bits of the port, for example. Imagine that you have set
> bit 1
> of the port, and this pin has a high capacitance on it, so it takes a
> significant time for the voltage on the output pin to reach a '1'
> state. The
> next instruction does a BSF on bit 2, but this is a R/M/W instruction
> so it
> reads bit 1, and finds it is not yet at a '1' state because of the
> rise time
> due to the capacitance on the pin load, so reads it as a '0'. It then
> gets
> written back as a '0' as the whole port is written, not just the bit
> being
> modified. For this reason it is generally recommended to have at
> least one
> instruction between consecutive port writes, or between a write, and
> a read
> that uses modified bits.
>
 An idea with be to use a D latch on the pins that are sensitive that
would latch data on the falling edge of the clock during the Q1 period
only.
 This is the only moment when one can sync data with the clock and not
affect a read or write in progress.
 Additional circuitry is required to separate this falling edge though.

Please tell me if it makes sense.


=====
ing. Andrei Boros
Centrul pt. Tehnologia Informatiei
Societatea Romana de Radiodifuziune

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