On 2002.01.09 06:39 James Paul wrote:
>  Peter,
>
>  I agree that an Emitter Follower circuit configuration be used, but

Oh.  I must have not made myself clear, because I would NOT use an emitter
follower.
You can't avoid the .7V Vbe drop, and since you would have to take the base
more
positive than the collector to get the emitter up to the collector voltage
I don't
think it can be done.

However its been along time since I did a solid state theory exam :-)

>  I don't agree with the ~.7 v drop across the transistor.  If the
>  transistor is saturated, and it should be, the drop across the
>  transistor (Vce [sat]) should be only about .2 V.   You can adjust
>  the Base resistor so that a high from a PIC pin will saturate the
>  transistor and cause Vce to be the above said .2V or so. And it
>  really doesn't amtter whether you use an NPN or a PNP, the Vce sat
>  is going to be about the same (not exactly the same though) provided
>  you choose your resistors correctly.  Not that with a PNP transistor,
>  it will be turned on with a logic low as opposed to a logic high with
>  the NPN.

I don't agree....  Using a common emitter PNP and pulling the base to
ground you can
saturate the transistor and then you can achive the Vce sat drop .

Peter

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