>Probably this is achieved by page-ing.
>Either by sending another address byte or toggling one
>of the address pins (A0).

Typically, there are 3 block select (or "chip select") pins (A0-A2) that are
used to define the device's address on the bus.  This allows up to eight 2K
devices on the same bus.  For large EEPROMs, these pins are usually not used
externally, but their functionality inside the chip is used.

The EEPROMs are structured to have memory addresses separated into 256-byte
blocks.  For larger memory devices, there are simply more blocks.  To access
a block, use the "chip select" or "block select" bits in the control byte
during a read or write operation.

For VERY large memory devices (more than 256K), the devices simply use HIGH
and LOW address bytes rather than blocks of memory.  I don't know how many
of these devices are on the market as of yet - Microchip's large memory
devices are listed as "Future Products."


I would imagine it would be simple to modify any I2C code to utilize either
multiple blocks or high and low address bytes.

--Andrew

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