Hi all !

It's correct to say :

1) if CCPR1L+CCP1X+CCP1Y > PR2*4 the Duty cycle of the PWM signal will =
be 100% ??????
2) if CCPR1L+CCP1X+CCP1Y =3D 0 the Duty cycle will be 0% ?????

DS31014A is not very clear:
 If TMR2 is a 8 bit timer acting as 10 bit counter with the 2 LSB =
comming from the Q cycle or prescaler and the PR2 is an 8 bit reg.
Can I say in that case (PWM mode 10 bit reg), the PR2 will compare only =
with the 8 MSB of the 10 bit counter what will be the same as a =
comparison between CCPR1L+CCP1X+CCP1Y and PR2*4 ????????

..... errrh, I hope someone could understand ... :-)

TIA,

Fabio Pereira

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