Serial comms with 1 start bit, eight data bits, and one stop bit aren't
that fussy about timing.  It automatically resynchronizes at every stop
bit/ start bit transition, so the message length doesn't matter.  In
theory you could be off by 10% and it would still work.  The character
length matters, so if you use 2 stop bits or fewer data bits the timing
is even more forgiving.  In practice I wouldn't drift farther than +/-5%
worst case, +/-3% is better.

Are you using a hardware or software UART?

Sherpa Doug

> -----Original Message-----
> From: Gennette, Bruce [mailto:bruce.gennette@TAFE.NSW.EDU.AU]
> Sent: Thursday, December 06, 2001 12:15 AM
> To: PICLIST@MITVMA.MIT.EDU
> Subject: [PIC]:Is it possible to adjust internal osc to 3.6864MHz?
>
>
> For short messages I think it should be possible to implement
> simple, low
> speed (1200/2400) RS-232 in chips that have an internal 4MHz (nominal)
> oscillator *IF* the osccal can be loaded with a correctly
> calculated value.
> At these low speeds it should be possible to identify and
> synchronise with a
> start bit and then read in a few bytes before losing
> synchronisation.  If
> messages are restricted to that size comms should be possible.
>
> Does anyone know if osccal can be adjusted to slow the chip
> down by about 8%
> (((4-3.6864)/4)*100) ?
>
> If it can, what is the formula to calculate the osccal value from the
> factory supplied osccal adjustment value ?
>
> If it can't what is the formula to 'drop' cycles to simulate
> 3.6864MHz when
> the chip is operating at 4MHz ? (nop every 12.5 instructions ?)
>
> Thanx in advance.
> Bye.
>
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